Diamond Rapids Is Not Just a 256-Core CPU — Intel Is Turning Xeon Into a Chiplet System
Diamond Rapids Is Not Just a 256-Core CPU — Intel Is Turning Xeon Into a Chiplet System¶
- Source: SemiVision
- Author: SEMIVISION
- Published: 2026-08-26T09:20:16+08:00
- URL: https://tspasemiconductor.substack.com/p/diamond-rapids-is-not-just-a-256
中文翻譯與英文原文（雙語）¶
(2) Diamond Rapids 不僅僅是 256 核心 CPU — Intel 正將 Xeon 轉型為小晶片系統 --- (2) Diamond Rapids Is Not Just a 256-Core CPU — Intel Is Turning Xeon Into a Chiplet System
Diamond Rapids Is Not Just a 256-Core CPU — Intel Is Turning Xeon Into a Chiplet System¶
Diamond Rapids 不僅僅是 256 核心 CPU — Intel 正將 Xeon 轉型為晶片粒系統
Original Article By SemiVision Research [Reading time: 10 mins]¶
原文作者：SemiVision Research [閱讀時間：10 分鐘]
Aug 26, 2026
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Diamond Rapids Is Not Just a 256-Core CPU — Intel Is Turning Xeon Into a Chiplet System
Diamond Rapids 不僅僅是一款 256 核心 CPU — Intel 正將 Xeon 轉型為晶片粒系統
Intel’s Diamond Rapids presentation at Hot Chips 2026 looks, at first glance, like another server-CPU specification update.
Intel 於 Hot Chips 2026 發表的 Diamond Rapids 簡報，乍看之下不過是另一場伺服器 CPU 規格更新。
Up to 256 performance cores
最多 256 個效能核心
1.28GB of last-level cache.
1.28GB 的最後一階快取記憶體。
Up to 1.6TB/s of memory bandwidth.
高達 1.6TB/s 的記憶體頻寬。
128 lanes of high-speed I/O.
128 條高速 I/O 通道。
Intel 18A-P compute silicon.
Intel 18A-P 運算矽晶。
Those numbers matter, but they are not the most important part of Diamond Rapids.
這些數字固然重要，但並非 Diamond Rapids 最關鍵的部分。
The bigger story is architectural.
更重大的變革在於架構層面。
Intel is effectively decomposing Xeon into a collection of compute chiplets, base tiles, fabric hubs, memory interfaces and I/O infrastructure, then rebuilding the processor through advanced packaging and high-bandwidth die-to-die links.
Intel 正將 Xeon 有效拆解為一組運算小晶片（chiplets）、基底瓦片（base tiles）、互連樞紐（fabric hubs）、記憶體介面與 I/O 基礎設施，再透過先進封裝技術與高頻寬晶片間連結，重新建構處理器。
This is increasingly what a high-end CPU looks like in the AI era.
這正是人工智慧時代高階 CPU 日益呈現的樣貌。
The server CPU is no longer a monolithic piece of silicon surrounded by memory controllers and PCIe interfaces. It is becoming a small computing system inside the package.
伺服器 CPU 已不再是周圍環繞著記憶體控制器與 PCIe 介面的單晶片矽元件，而是逐漸演變為封裝內的小型運算系統。
And that has major implications for foundry economics, hybrid bonding, advanced substrates, memory, testing and the broader semiconductor supply chain.
此轉變對晶圓代工經濟、混合鍵結（Hybrid Bonding）、先進基板、記憶體、測試以及更廣泛的半導體供應鏈產生重大影響。
4月24日4 月 24 日
4月21日4 月 21 日
Below we will share:以下我們將分享：
Hybrid Bonding Is Becoming Part of CPU Architecture
混合鍵結（Hybrid Bonding）正成為 CPU 架構的一部分
Intel’s “Fan-Out Fabric” Is Not Fan-Out Packaging
Intel 的「扇出式互連架構」並非扇出式封裝
CPUs Are Becoming the Traffic Controllers of AI Systems
CPU 正成為 AI 系統的流量控制器
Diamond Rapids: 256 Cores Is the Headline, 22 Active Tiles Are the Story
Diamond Rapids：256 核心是頭條，22 個作用中的晶片才是重點
Intel disclosed a high-end Diamond Rapids configuration consisting of:
Intel 揭露了一款高階 Diamond Rapids 組態，其組成包括：
16 Core Chiplets16 核心晶片粒
4 Base Tiles4 個基礎晶粒
2 Fabric Hub Tiles2 個 Fabric Hub 晶粒
The Core Chiplets are manufactured using Intel 18A-P, while other functions are implemented on Intel 3-class process technologies.
核心晶片粒採用 Intel 18A-P 製程製造，而其他功能則在 Intel 3 級製程技術上實現。
This is the first key architectural point.
這是第一個關鍵的架構重點。
Intel does not need every transistor in Diamond Rapids to be manufactured on its most advanced process node.
Intel 不需要將 Diamond Rapids 中的每一個電晶體都製造在其最先進的製程節點上。
CPU cores benefit significantly from leading-edge transistor density and performance. Memory interfaces, I/O, fabric logic and other functions do not necessarily have the same economic justification.
CPU 核心能顯著受益於最先進的電晶體密度與效能，但記憶體介面、I/O、結構邏輯及其他功能未必具備相同的經濟合理性。
So Intel can reserve 18A-P for the blocks where it creates the most value.
因此，Intel 可以將 18A-P 製程保留用於能創造最大價值的區塊。
This is the basic economic logic behind chiplets:
這就是晶片粒（chiplet）背後的基礎經濟邏輯：
Do not manufacture every transistor on the most expensive wafer.
並非所有電晶體都必須在最昂貴的晶圓上製造。
A monolithic design forces compute, cache, I/O, memory controllers and other functions onto the same process node.
單片式設計會將運算、快取、I/O、記憶體控制器及其他功能全部整合到同一製程節點上。
Chiplets allow Intel to optimize process technology block by block.
Chiplet 技術讓英特爾能夠針對每個區塊優化製程技術。
Leading-edge wafers become increasingly expensive as lithography complexity, mask costs, defect sensitivity and design complexity rise. Meanwhile, very large monolithic dies suffer from deteriorating yield.
隨著微影技術複雜度、光罩成本、缺陷敏感度及設計複雜度不斷上升，先進製程晶圓的成本也日益高昂。與此同時，超大尺寸的單晶片（monolithic die）面臨良率惡化的問題。
Breaking a large processor into smaller dies improves manufacturing flexibility and potentially improves silicon yield.
將大型處理器拆解為較小的晶粒，可提升製造靈活性，並有望改善矽晶良率。
But there is a catch.
但其中存在一個關鍵挑戰。
The yield problem does not disappear.
良率問題並未消失。
It moves into packaging.它轉移到了封裝環節。
Hybrid Bonding Is Becoming Part of CPU Architecture
混合鍵結正成為 CPU 架構的一部分
Diamond Rapids illustrates an important transition in semiconductor design.
Diamond Rapids 說明了半導體設計的一項重要轉變。
Advanced packaging is no longer something that happens after architecture is finished.
先進封裝已不再是架構完成後才進行的步驟。
2025年7月13日2025 年 7 月 13 日
Packaging is part of the architecture.
封裝已是架構的一部分。
Intel connects Core Chiplets to Base Tiles using Foveros 3D Direct and a Hybrid Bonding Interface, or HBI.
英特爾透過 Foveros 3D Direct 與混合鍵結介面（HBI），將核心小晶片（Core Chiplets）連接至基底晶粒（Base Tiles）。
At the same time, other die-to-die connections use substrate copper links and UCIe-S.
同時，其他晶片對晶片的連接則使用基板銅連結與 UCIe-S。
Diamond Rapids therefore contains multiple interconnect hierarchies inside one CPU package.
因此，Diamond Rapids 在單一 CPU 封裝內包含了多層次的互連架構。
At very short distances, hybrid bonding provides extremely dense vertical interconnect.
在極短距離下，混合鍵合（hybrid bonding）可提供極為密集的垂直互連。
At longer package-level distances, UCIe and substrate routing provide horizontal connectivity between different functional blocks.
在較長的封裝層級距離上，UCIe 與基板佈線則提供不同功能區塊之間的水平連接。
This is fundamentally different from the traditional model:
這與傳統模式有根本性的不同：
Large CPU die → flip-chip bumps → ABF substrate → motherboard
大型 CPU 晶粒 → 覆晶焊球 → ABF 基板 → 主機板
The new model increasingly becomes:
新模式正逐漸演變為：
Compute die → hybrid bonding → base die → package interconnect → fabric die → substrate → motherboard
運算晶粒 → 混合鍵結 → 基底晶粒 → 封裝互連 → 交換器晶粒 → 基板 → 主機板
Every additional layer creates new manufacturing requirements.
每一層的增加都會帶來新的製造需求。
Bonding accuracy matters.
接合精度至關重要。
Surface planarity matters.
表面平整度至關重要。
Copper recess and dielectric uniformity matter.
銅凹陷與介電質均勻性至關重要。
Die thickness matters.晶圓厚度至關重要。
Warpage matters.翹曲問題至關重要。
Known-good-die screening matters.
已知良品晶粒篩選至關重要。
Temporary bonding and debonding matter.
臨時鍵合與解鍵合至關重要。
Substrate routing density matters.
基板佈線密度至關重要。
Thermal expansion mismatch matters.
熱膨脹係數不匹配至關重要。
The semiconductor industry has spent decades optimizing wafer yield.
半導體產業已花費數十年時間優化晶圓良率。
The next optimization problem is increasinglysystem yield.
下一個最佳化問題是系統良率日益重要。
For a highly disaggregated processor, the economics begin to look more like:
對於高度分離式的處理器，其經濟模型開始更接近如下：
System Yield = Die Yield × Bonding Yield × Assembly Yield × Substrate Yield × Test Yield
系統良率 = 晶粒良率 × 接合良率 × 組裝良率 × 基板良率 × 測試良率
The exact equation is more complicated, because redundancy, repair and binning can alter the result.
實際公式更為複雜，因為冗餘設計、修復機制與分級（binning）都會影響最終結果。
But the principle is clear.
但原則很明確。
Once a package contains dozens of active semiconductor components, small yield losses at each assembly step compound rapidly.
一旦封裝內包含數十個主動半導體元件，每個組裝步驟的微小良率損失將會迅速累積。
This is why advanced packaging equipment and materials are becoming strategic semiconductor technologies rather than commodity back-end processes.
這正是先進封裝設備與材料正從傳統的後段製程商品，轉變為具戰略意義的半導體技術之原因。
2025年5月1日2025 年 5 月 1 日
Intel’s “Fan-Out Fabric” Is Not Fan-Out Packaging
Intel 的「扇出式互連架構」並非扇出式封裝
One term in Intel’s presentation may create confusion for packaging investors.
Intel 簡報中的一個術語可能會讓封裝領域的投資者產生混淆。
Diamond Rapids introduces aFan-out Fabric Architecture.
Diamond Rapids 引入了扇出式互連架構（Fan-out Fabric Architecture）。
This does not mean fan-out wafer-level packaging.
這並不代表扇出型晶圓級封裝。
Intel is describing the topology of the processor fabric.
英特爾正在描述處理器互連架構的拓撲結構。
The architecture separates scalable Compute Building Blocks from centralized Fabric Hubs.
此架構將可擴展的運算建構模組（Compute Building Blocks）與集中式的互連樞紐（Fabric Hubs）分離。
The Compute Building Blocks contain primarily:
運算建構模組主要包含：
CPU coresCPU 核心
L2 cacheL2 快取
shared LLC共享 LLC
The Fabric Hub contains functions such as:
Fabric Hub 包含以下功能：
DDR interfacesDDR 介面
memory controllers記憶體控制器
memory interconnect記憶體互連
I/O PHYsI/O 實體層
I/O cacheI/O 快取
accelerators加速器
snoop filters窺探過濾器
encryption加密
other system fabric functions
其他系統互連功能
This separation is strategically important.
此種分離具有戰略重要性。
Traditional server CPUs tend to scale compute and infrastructure together.
傳統伺服器 CPU 傾向於將運算能力與基礎設施一同擴展。
More cores generally require increasingly large SoCs with replicated or increasingly complex internal fabrics.
更多的核心通常需要越來越大的 SoC，並伴隨著重複或日益複雜的內部互連架構。
Intel is instead moving toward:
英特爾則正朝向以下方向發展：
Scalable Compute Blocks + Centralized Memory and I/O Infrastructure
可擴展運算區塊 + 集中式記憶體與 I/O 基礎設施
That gives Intel more flexibility in how future Xeon products are assembled.
這讓英特爾在未來 Xeon 產品的組裝方式上擁有更大的靈活性。
Need more cores?需要更多核心嗎？
Add or modify compute blocks.
新增或修改運算區塊。
Need a different I/O configuration?
需要不同的 I/O 配置嗎？
Change the fabric architecture.
變更互連架構。
Need additional memory bandwidth?
需要更多記憶體頻寬嗎？
Modify the memory subsystem without necessarily redesigning every compute tile.
修改記憶體子系統，而不必重新設計每個運算晶片。
This is not infinitely modular — physical layout, latency, coherency and power constraints remain severe — but it moves Xeon closer to a composable architecture.
這並非無限模組化——實體佈局、延遲、一致性與功耗限制依然嚴峻——但這讓 Xeon 更接近可組合式架構。
That matters because AI infrastructure itself is becoming composable.
這點至關重要，因為 AI 基礎設施本身正變得可組合化。
CPUs Are Becoming the Traffic Controllers of AI Systems
CPU 正成為 AI 系統的流量控制器
The conventional AI narrative says GPUs are replacing CPUs.
傳統的 AI 論述認為 GPU 正在取代 CPU。
That interpretation is too simplistic.
這種解讀過於簡化。
GPUs are taking a larger share of arithmetic-intensive compute, particularly matrix multiplication.
GPU 正佔據更多需要大量算術運算的計算資源，尤其是矩陣乘法。
But AI servers are simultaneously becoming much more complicated systems.
但與此同時，AI 伺服器正變為更加複雜的系統。
A modern AI infrastructure node must handle:
現代 AI 基礎設施節點必須處理：
network traffic網路流量
storage traffic儲存流量
inference orchestration推論協調
retrieval檢索
vector databases向量資料庫
memory management記憶體管理
security安全性
scheduling排程
preprocessing預處理
decompression解壓縮
metadata operations中繼資料作業
virtualization虛擬化
telemetry遙測
distributed system coordination
分散式系統協調
Much of this work remains CPU-centric.
這項工作的大部分仍以 CPU 為核心。
Agentic AI may make this even more important.
代理式 AI 可能讓這一點變得更為重要。
An AI agent does not simply execute one enormous matrix multiplication operation.
AI 代理並非單純執行一次龐大的矩陣乘法運算。
It can repeatedly query databases, invoke tools, call external services, retrieve memory, generate tokens, execute code and coordinate multiple models.
它能夠反覆查詢資料庫、呼叫工具、調用外部服務、檢索記憶體、生成 token、執行程式碼，並協調多個模型。
The result is a heterogeneous workload.
其結果是一種異質性工作負載。
The GPU handles dense accelerated compute.
GPU 負責處理高密度的加速運算。
The CPU manages much of the surrounding system.
CPU 則管理周邊系統的大部分運作。
This helps explain several of Diamond Rapids’ architectural priorities.
這有助於解釋 Diamond Rapids 的幾項架構優先事項。
Intel disclosed:Intel 揭露：
Up to 256 high-performance cores
高達 256 個高效能核心
The objective is straightforward: more host-side parallelism.
目標很明確：提升主機端的平行處理能力。
1.28GB of Last Level Cache
1.28GB 的最後一層快取
Large shared cache helps reduce expensive memory accesses and benefits infrastructure workloads with large working sets.
大型共享快取有助於減少昂貴的記憶體存取，並讓具有大型工作集的基礎設施工作負載受益。
Approximately 1.6TB/s memory bandwidth
約 1.6TB/s 的記憶體頻寬
Intel is targeting 12,800MT/s MRDIMM support.
Intel 的目標是支援 12,800MT/s 的 MRDIMM。
CPU memory bandwidth is becoming increasingly important as core counts continue to rise.
隨著核心數量持續增加，CPU 記憶體頻寬變得日益重要。
128 high-speed I/O lanes128 條高速 I/O 通道
High-bandwidth connectivity is critical as the CPU sits beside GPUs, NICs, DPUs, storage and CXL devices.
當 CPU 與 GPU、NIC、DPU、儲存裝置及 CXL 設備並列時，高頻寬連線至關重要。
Intel also continues supporting AMX and AVX 10.2, including lower-precision AI formats.
Intel 也持續支援 AMX 與 AVX 10.2，包含較低精度的 AI 格式。
The CPU is therefore not trying to become a GPU.
因此，CPU 並非試圖轉變為 GPU。
It is becoming the orchestration layer surrounding the GPU.
它正成為環繞 GPU 的協調層。
Memory Bandwidth Is Quietly Becoming One of the Most Important CPU Metrics
記憶體頻寬正悄然成為最重要的 CPU 指標之一
The core-count race creates an obvious problem.
核心數量的競賽帶來了一個顯而易見的問題。
Adding cores is relatively easy compared with feeding those cores with data.
與為這些核心提供數據相比，增加核心數量相對容易。
A 256-core processor with inadequate memory bandwidth becomes a very expensive collection of stalled execution units.
若記憶體頻寬不足，256 核心的處理器只會成為一組昂貴卻停滯的執行單元集合。
Diamond Rapids therefore emphasizes up to approximately 1.6TB/s of memory bandwidth.
因此，Diamond Rapids 強調提供高達約 1.6TB/s 的記憶體頻寬。
The same trend is visible elsewhere.
同樣的趨勢在其他地方也清晰可見。
Arm’s AGI CPU presentation at Hot Chips highlighted:
Arm 於 Hot Chips 發表的 AGI CPU 簡報重點如下：
up to 136 Arm Neoverse V3 cores
最高可達 136 顆 Arm Neoverse V3 核心
2MB dedicated L2 cache per core
每核心配備 2MB 專屬 L2 快取
frequencies up to 3.7GHz頻率最高可達 3.7GHz
96 lanes of PCIe Gen6
96 條 PCIe Gen6 通道
CXL 3.0
DDR5-8800
approximately 6GB/s memory bandwidth per core
每核心約 6GB/s 的記憶體頻寬
up to 6TB memory capacity per chip
每顆晶片最高可達 6TB 記憶體容量
sub-100ns memory latency targets
目標記憶體延遲低於 100 奈秒
a dual-chiplet design雙小晶片（chiplet）設計
TSMC 3nm manufacturing台積電 3 奈米製程
300W TDP
Intel and Arm are implementing different architectures, but they are attacking the same physical constraint:
Intel 與 Arm 正在實作不同的架構，但兩者都在應對相同的物理限制：
How do you scale compute faster than power, memory latency and I/O bottlenecks scale?
如何在運算能力加速的同時，避免功耗、記憶體延遲與 I/O 瓶頸同步惡化？
Shrinking the transistor is no longer enough.
縮小電晶體已不再足夠。
The solution increasingly requires four technologies simultaneously:
解決方案日益需要同時整合四項技術：
Chiplets + Advanced Packaging + High-Speed Memory + High-Bandwidth Fabric
Chiplets + 先進封裝 + 高速記憶體 + 高頻寬互連架構
That combination is becoming the real foundation of server CPU scaling.
此組合正成為伺服器 CPU 擴展的真正基礎。
The CPU Is Starting to Look More Like a GPU Package
CPU 開始看起來更像 GPU 封裝
There is another important convergence happening.
另一項重要的匯流趨勢正在發生。
Historically, advanced packaging innovation was most visible in GPUs and AI accelerators.
歷史上，先進封裝的創新最顯著地體現在 GPU 和 AI 加速器上。
HBM forced GPU vendors to integrate logic dies with massive memory interfaces.
HBM 迫使 GPU 廠商將邏輯晶片與大規模記憶體介面整合。
Large AI accelerators pushed the industry toward silicon interposers, RDL interposers, bridges and complex 2.5D packaging.
大型 AI 加速器推動產業朝向矽中介層、RDL 中介層、橋接器以及複雜的 2.5D 封裝發展。
CPUs did not face the same pressure.
CPU 並未面臨相同的壓力。
That is changing.情況正在改變。
A 256-core CPU with dozens of functional dies, 1TB-class cache, terabytes-per-second memory bandwidth and hundreds of high-speed I/O links starts facing many of the same packaging problems as AI accelerators.
一款擁有數十個功能晶片、256 核心、TB 級快取、每秒 TB 級記憶體頻寬以及數百條高速 I/O 連結的 CPU，開始面臨與 AI 加速器類似的封裝挑戰。
The package becomes a system.
封裝已演變為一個系統。
The difference is that CPU architectures must also maintain extremely complex cache coherency across many processing blocks.
不同之處在於，CPU 架構還必須在眾多處理區塊之間維持極為複雜的快取一致性。
This means latency and interconnect design become even more critical.
這意味著延遲與互連設計變得更加關鍵。
We expect the distinction between “CPU packaging” and “AI accelerator packaging” to continue narrowing.
我們預期「CPU 封裝」與「AI 加速器封裝」之間的區別將持續縮小。
The technologies will not be identical, but many of the same suppliers can benefit.
這些技術不會完全相同，但許多相同的供應商仍能從中受益。
Advanced Packaging Value Content Keeps Rising
先進封裝的價值持續攀升
Diamond Rapids has obvious implications for Intel Foundry.
Diamond Rapids 對英特爾晶圓代工（Intel Foundry）具有顯著的影響。
But the supply-chain implications extend much further.
但其對供應鏈的影響遠不止於此。
As server CPUs become increasingly disaggregated, more semiconductor value migrates from front-end transistor scaling into integration.
隨著伺服器 CPU 日益走向分離式架構，更多的半導體價值正從前端電晶體微縮轉向整合技術。
Potential beneficiaries include:
潛在受益者包括：
Hybrid bonding equipment混合鍵合設備
Wafer preparation, bonding, alignment, surface activation and inspection become increasingly important.
晶圓製備、鍵合、對準、表面活化與檢測變得日益重要。
Advanced substrates先進基板
More dies and more high-speed connections increase routing complexity and package size.
更多的晶粒與更多的高速連接會增加佈線複雜度與封裝尺寸。
Dielectric and build-up materials
介電質與堆疊材料
Electrical performance, low loss, dimensional stability and warpage become increasingly important as substrate complexity rises.
隨著基板複雜度提升，電氣性能、低損耗、尺寸穩定性與翹曲控制變得日益重要。
Temporary bonding materials
臨時接合材料
Thin dies and 3D integration create additional handling requirements.
薄晶粒與 3D 整合帶來額外的處理需求。
Metrology and inspection計量與檢測
Hybrid bonding has much tighter defect tolerance than conventional bump-based packaging.
混合鍵合技術對缺陷的容忍度遠高於傳統的凸塊式封裝。
Advanced test先進測試
The industry must test individual dies, bonded structures and complete packages without allowing test costs to explode.
產業必須測試個別晶粒、接合結構與完整封裝，同時避免測試成本急劇攀升。
Thermal management熱管理
Stacking active silicon vertically improves interconnect density but complicates heat removal.
垂直堆疊主動式矽晶層可提升互連密度，卻也使散熱更為複雜。
This is why the packaging content per high-end processor can grow even if wafer-area growth slows.
這正是為何即使晶圓面積成長趨緩，每顆高階處理器的封裝內容仍持續增加。
The Real Battle Is No Longer Intel vs Arm Core Count
真正的戰場已不再是英特爾與 Arm 的核心數量之爭
It is tempting to frame Hot Chips as another CPU benchmark competition.
將 Hot Chips 視為另一場 CPU 基準測試競賽固然誘人。
Intel: 256 cores.Intel：256 核心。
Arm: 136 cores.Arm：136 核心。
Which one wins?誰會勝出？
That comparison misses the structural change.
該比較忽略了結構性的變革。
The competitive unit is shifting from the CPU core to thecomputing system.
競爭單位正從 CPU 核心轉向整個運算系統。
Future server CPU comparisons increasingly need to include:
未來伺服器 CPU 的比較將日益需要納入以下指標：
MetricWhy It MattersCPU core performanceTraditional compute performancePerformance per wattData-center power constraintMemory bandwidthAbility to feed hundreds of coresMemory latencyCritical for database and infrastructure workloadsLLC capacityReduces DRAM trafficPCIe/CXL bandwidthGPU, NIC, storage and memory connectivityDie-to-die bandwidthChiplet scaling efficiencyPackaging topologyDetermines achievable system sizePackage yieldIncreasingly important to total costCooling requirementsLimits rack-level density
指標為何重要 CPU 核心效能傳統運算效能每瓦特效能資料中心電力限制記憶體頻寬餵養數百個核心的能力記憶體延遲對資料庫與基礎設施工作負載至關重要 LLC 容量減少 DRAM 流量 PCIe/CXL 頻寬 GPU、NIC、儲存裝置與記憶體的連接性晶粒間頻寬晶片小塊（chiplet）擴展效率封裝拓撲決定可實現的系統規模封裝良率對總成本日益重要散熱需求限制機架層級密度
Core count becomes only one variable.
核心數量僅成為其中一個變數。
This is the same transition the GPU industry experienced.
這正是 GPU 產業曾經經歷過的轉型。
NVIDIA’s advantage is no longer simply the GPU die.
NVIDIA 的優勢已不再僅限於 GPU 晶片本身。
It is GPU + HBM + NVLink + NVSwitch + networking + software + rack architecture.
而是 GPU + HBM + NVLink + NVSwitch + 網路 + 軟體 + 機架架構的整體整合。
Server CPUs are beginning to move in the same direction.
伺服器 CPU 也正開始朝相同方向發展。
Wildcat Lake Shows the Same Trend at the Other End of the Market
Wildcat Lake 在市場的另一端也呈現出相同趨勢
Intel also presented its Core Series 3 platform, Wildcat Lake, at Hot Chips 2026.
英特爾也在 Hot Chips 2026 上發表了其 Core Series 3 平台 Wildcat Lake。
Wildcat Lake targets value-oriented mobile and edge systems derived from technologies developed around Panther Lake.
Wildcat Lake 鎖定以 Panther Lake 周邊開發技術為基礎的價值導向行動與邊緣系統。
Intel highlights up to roughly 40 platform TOPS across CPU, GPU and NPU resources while targeting significantly lower processor power.
Intel 強調，在 CPU、GPU 和 NPU 資源整合下，平台可提供高達約 40 TOPS 的運算效能，同時大幅降低處理器功耗。
The workloads are very different from Diamond Rapids.
其工作負載與 Diamond Rapids 截然不同。
But the architectural philosophy is similar.
但兩者的架構理念卻十分相似。
There is no longer one universal processor optimized for every workload.
不再有單一通用處理器能針對所有工作負載進行最佳化。
Compute is becoming heterogeneous.
運算正走向異質化。
Cloud servers use combinations of CPUs, GPUs, DPUs and accelerators.
雲端伺服器採用 CPU、GPU、DPU 與加速器的組合。
PCs combine CPU, GPU and NPU engines.
PC 結合了 CPU、GPU 和 NPU 引擎。
Edge systems balance AI performance against power, cost and latency.
邊緣系統在 AI 效能、功耗、成本與延遲之間取得平衡。
The processor market is fragmenting, but the underlying trend is consistent:
處理器市場正趨於碎片化，但底層趨勢始終一致：
More specialized compute blocks connected by increasingly sophisticated fabrics.
更多專用運算區塊透過日益精複雜的互連架構相互連接。
SemiVision View: Process Builds the Die. Packaging Builds the System.
SemiVision 觀點：製程打造晶粒，封裝建構系統。
For most of semiconductor history, performance leadership was closely tied to process-node leadership.
在半導體歷史的大部分時間裡，效能領先與製程節點領先緊密相連。
Move to the next node.
移至下一個節點。
Increase transistor density.
提高電晶體密度。
Increase frequency.提高頻率。
Add more cores.增加更多核心。
Repeat.重複。
That model is not dead, but it is no longer sufficient.
該模式並未消亡，但已不再足夠。
Diamond Rapids demonstrates the new reality.
Diamond Rapids 展現了新的現實。
Intel still needs 18A-P.Intel 仍需 18A-P。
Leading-edge transistors remain critical.
先進製程電晶體仍然至關重要。
But 18A-P alone cannot create a 256-core server platform.
但僅靠 18A-P 並無法打造具備 256 核心的伺服器平台。
Intel also needs Intel 3-class base and fabric dies, Foveros Direct, hybrid bonding, UCIe, advanced substrates, high-speed MRDIMM memory and increasingly sophisticated package testing.
Intel 還需要 Intel 3 等級的基底與互連晶片、Foveros Direct、混合鍵合（hybrid bonding）、UCIe、先進基板、高速 MRDIMM 記憶體，以及日益精進的封裝測試技術。
The bottleneck is moving from the transistor toward the integration of many different technologies.
瓶頸正從電晶體轉向多項不同技術的整合。
This is the strategic shift investors should pay attention to.
這是投資者應關注的戰略轉變。
Process technology determines what one die can do.
製程技術決定了單一晶片所能實現的功能。
Packaging, memory and fabric determine how large the system can become.
封裝、記憶體與互連架構決定了系統可擴展的規模。
Diamond Rapids matters because Intel is no longer designing Xeon as one giant CPU.
Diamond Rapids 之所以重要，是因為 Intel 不再將 Xeon 設計為一顆巨大的單體 CPU。
Intel is designing a chiplet computing system that happens to fit inside a CPU socket.
英特爾正在設計一個晶片運算系統，而它恰好能裝入 CPU 插槽中。
And that may be a much better framework for understanding the next decade of server semiconductor competition.
這或許是理解未來十年伺服器半導體競爭格局更佳的框架。
Thanks for reading SEMIVISION @_@! This post is public so feel free to share it.
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