HBF: As NAND Adopts an HBM-Like Architecture, the AI Memory Hierarchy Is Being Redefined
HBF: As NAND Adopts an HBM-Like Architecture, the AI Memory Hierarchy Is Being Redefined¶
- Source: SemiVision
- Author: SEMIVISION
- Published: 2026-08-24T11:18:58+08:00
- URL: https://tspasemiconductor.substack.com/p/hbf-as-nand-adopts-an-hbm-like-architecture
中文翻譯與英文原文（雙語）¶
(2) HBF：隨著 NAND 採用類似 HBM 的架構，AI 記憶體階層正被重新定義 --- (2) HBF: As NAND Adopts an HBM-Like Architecture, the AI Memory Hierarchy Is Being Redefined
HBF: As NAND Adopts an HBM-Like Architecture, the AI Memory Hierarchy Is Being Redefined¶
HBF：隨著 NAND 採用類似 HBM 的架構，AI 記憶體階層正被重新定義
Original Article By SemiVision Research [Reading time: 11 mins]¶
原文作者：SemiVision Research [閱讀時間：11 分鐘]
Aug 24, 2026
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A new direction is emerging in AI infrastructure in 2026:NAND flash is no longer being treated solely as storage inside SSDs. Instead, it is beginning to evolve toward a near-compute, high-bandwidth, high-capacity memory tier.One of the most representative technologies behind this transition isHBF, or High Bandwidth Flash, currently being advanced by Sandisk and SK hynix.
2026 年，AI 基礎設施正湧現新的發展方向：NAND 快閃記憶體不再僅被視為固態硬碟（SSD）內的儲存裝置，而是開始演進為靠近運算單元、具備高頻寬與大容量特性的記憶體層級。推動此轉型最具代表性的技術之一，便是由 Sandisk 與 SK hynix 共同推進的 HBF（High Bandwidth Flash，高頻寬快閃記憶體）。
The simplest way to understand HBF is to think of it as applying an HBM-like architecture to NAND flash. Traditional NAND offers extremely high capacity, low cost per bit, and non-volatility, but its bandwidth and latency are far inferior to DRAM. HBM, by contrast, vertically stacks multiple DRAM dies using TSVs, micro-bumps, a base or logic die, and ultra-wide I/O interfaces to deliver TB/s-class memory bandwidth directly adjacent to GPUs and AI accelerators.
理解 HBF 最簡單的方式，是將其視為將類似 HBM 的架構應用於 NAND 快閃記憶體。傳統的 NAND 提供極高的容量、每位元低成本以及非揮發性特性，但其頻寬與延遲遠遜於 DRAM。相較之下，HBM 透過 TSV、微凸塊、基底或邏輯晶片，以及超寬 I/O 介面，垂直堆疊多個 DRAM 晶粒，從而直接在 GPU 與 AI 加速器旁提供 TB/s 等級的記憶體頻寬。
HBF attempts to bring some of these architectural principles to NAND. Rather than treating NAND simply as block storage sitting behind an SSD controller and PCIe interface, HBF uses highly parallel interfaces, 3D stacking, advanced packaging, and high-speed die-to-die connectivity to move flash much closer to the processor.
HBF 試圖將這些架構原則應用於 NAND。HBF 不再將 NAND 單純視為位於 SSD 控制器和 PCIe 介面後端的區塊儲存裝置，而是採用高度並行的介面、3D 堆疊、先進封裝以及高速晶片對晶片（die-to-die）連接技術，使快閃記憶體更靠近處理器。
Sandisk had already introduced its HBF architecture at its 2025 Investor Day. The concept places vertically stacked NAND dies above a logic die, with TSVs and micro-bumps providing dense vertical interconnects and a PHY at the bottom of the package connecting HBF to GPUs, CPUs, TPUs, or other processors. The fundamental objective is to push flash bandwidth much closer to the range required by AI accelerators while maintaining roughly an order of magnitude greater capacity than HBM.
Sandisk 已在 2025 年投資人日發表其 HBF 架構。此概念將垂直堆疊的 NAND 晶粒置於邏輯晶粒之上，透過 TSV 與微凸塊提供高密度的垂直互連，並在封裝底部設置 PHY，以將 HBF 連接至 GPU、CPU、TPU 或其他處理器。其根本目標是將快閃記憶體的頻寬提升至接近 AI 加速器所需的範圍，同時維持約比 HBM 高一個數量級的容量。
By FMS 2026, HBF had progressed beyond a proprietary product concept and entered the early stages of industry standardization. Sandisk and SK hynix have been working through the Open Compute Project on the HBF specification, with Google and Tenstorrent also participating in the ecosystem. This suggests that HBF is gradually evolving from a NAND-vendor initiative into a broaderAI memory ecosystem.
到了 2026 年 FMS 大會，HBF 已超越專屬產品的概念，邁入產業標準化的初期階段。Sandisk 與 SK hynix 一直透過 Open Compute Project 推動 HBF 規格制定，Google 和 Tenstorrent 也參與此生態系。這顯示 HBF 正逐漸從 NAND 供應商主導的計畫，演變為更廣泛的 AI 記憶體生態系。
We will share the following topics
我們將分享以下主題
The AI Memory Problem Is Shifting from Pure Bandwidth to Bandwidth × Capacity × Cost
AI 記憶體的挑戰正從單純的頻寬，轉向「頻寬 × 容量 × 成本」的綜合考量
Why Could 4TB of HBF with Four GPUs Approach the Throughput of Eight GPUs with HBM?
為何搭載 4TB HBF 的四顆 GPU，其吞吐量能接近配備 HBM 的八顆 GPU？
From the HBM Shortage to the AI Memory Hierarchy
從 HBM 短缺到 AI 記憶體階層架構
Looking ahead, we will continue to closely track the key memory technology developments presented atHot Chips 2026, with particular focus on the perspectives and roadmaps ofSK hynix, Samsung Electronics, and Micron. Our research will examine not only the evolution of HBM—including HBM4, HBM4E and next-generation high-bandwidth memory—but also the broader restructuring of the AI memory hierarchy, including 3D-stacked DRAM, HBF, CXL-based memory expansion, advanced packaging, logic-base-die integration, bandwidth scaling, power efficiency, and memory capacity. As AI accelerators increasingly face both the Memory Wall and growing capacity requirements, competition among the three major memory suppliers is moving beyond conventional DRAM technology towardsystem-level memory architecture. We will therefore continue monitoring how SK hynix, Samsung, and Micron position their technologies within next-generation GPU and AI ASIC platforms, and how their respective strategies could reshape the future AI memory ecosystem and supply chain.
展望未來，我們將持續密切追蹤 Hot Chips 2026 所發表的關鍵記憶體技術發展，特別聚焦於 SK hynix、Samsung Electronics 與 Micron 的觀點與路線圖。我們的研究不僅將探討 HBM 的演進（包括 HBM4、HBM4E 及下一代高頻寬記憶體），更將深入分析 AI 記憶體階層架構的全面重組，涵蓋 3D 堆疊 DRAM、HBF、基於 CXL 的記憶體擴充、先進封裝、邏輯基底晶片整合、頻寬擴展、電源效率以及記憶體容量等議題。隨著 AI 加速器日益面臨「記憶體牆」與不斷增長的容量需求，三大記憶體供應商之間的競爭已超越傳統 DRAM 技術，轉向系統層級的記憶體架構。因此，我們將持續監測 SK hynix、Samsung 與 Micron 如何在下一代 GPU 與 AI ASIC 平台中定位其技術，並評估其各自策略如何重塑未來的 AI 記憶體生態系與供應鏈。
The AI Memory Problem Is Shifting from Pure Bandwidth to Bandwidth × Capacity × Cost
AI 記憶體問題正從單純的頻寬轉向「頻寬 × 容量 × 成本」的綜合考量
The first step in understanding HBF is recognizing that it is not simply “faster NAND.”
理解 HBF 的第一步，是認知到它並非單純的「更快 NAND」。
During AI training, GPUs must continuously access massive amounts of tensor data, making HBM’s extremely high bandwidth essential. However, as AI infrastructure increasingly shifts toward large-scale inference, the memory problem is changing.
在 AI 訓練期間，GPU 必須持續存取大量張量數據，這使得 HBM 極高的頻寬至關重要。然而，隨著 AI 基礎設施日益轉向大規模推論，記憶體面臨的挑戰也正發生變化。
Model parameters, KV cache, long-context data, embeddings, RAG databases, agent states, metadata, and other intermediate datasets can create enormous memory-capacity requirements.
模型參數、KV 快取、長上下文數據、嵌入向量、RAG 資料庫、代理狀態、中繼資料以及其他中間數據集，都可能產生龐大的記憶體容量需求。
The problem is straightforward:
問題很明確：
Putting all of this data into HBM is economically inefficient and increasingly difficult to scale.
將所有這些資料放入 HBM 在經濟上效率不彰，且日益難以擴展。
Future AI servers are therefore unlikely to rely on a simple SRAM → HBM → DDR → SSD hierarchy. Instead, additional memory tiers are likely to emerge between these layers, each optimized for a different combination of bandwidth, latency, capacity, persistence, power consumption, and cost.
因此，未來的 AI 伺服器不太可能依賴簡單的 SRAM → HBM → DDR → SSD 階層架構。相反地，這些層級之間可能會出現額外的記憶體層級，每一層都針對頻寬、延遲、容量、持久性、功耗和成本的不同組合進行最佳化。
At FMS 2026, SK hynix presented an especially interesting framework for this emerging memory hierarchy.
在 FMS 2026 展會上，SK hynix 提出了一個特別引人注目的新興記憶體階層架構框架。
G0.5: 3D-Stacked DRAMG0.5：3D 堆疊 DRAM
This tier sits even closer to the processor than conventional HBM and uses vertically stacked DRAM to deliver extremely high bandwidth approaching SRAM-class performance while retaining DRAM-level capacity.
此層級比傳統 HBM 更靠近處理器，並採用垂直堆疊的 DRAM，提供極高的頻寬，接近 SRAM 等級的效能，同時保留 DRAM 等級的容量。
G1: HBMG1：HBM
HBM remains the primary high-performance memory for today’s AI GPUs and accelerators, offering exceptional bandwidth and relatively low latency. Its primary limitations are cost, capacity, packaging complexity, and supply constraints.
HBM 仍是當今 AI GPU 與加速器的主要高效能記憶體，提供極高的頻寬與相對較低的延遲。其主要限制在於成本、容量、封裝複雜度以及供應瓶頸。
G1.5: HBFG1.5：HBF
HBF sits below HBM in the hierarchy but aims to provide hundreds of gigabytes to potentially terabytes of capacity while maintaining hundreds of GB/s to TB/s-class aggregate bandwidth.
HBF 在記憶體階層中位於 HBM 之下，旨在提供數百 GB 至潛在 TB 級的容量，同時維持數百 GB/s 至 TB/s 等級的總聚合頻寬。
G2.5: CXL Pooled MemoryG2.5：CXL 池化記憶體
CXL memory extends the hierarchy further toward multi-terabyte capacities. Its primary objective is scalable, shareable, and cost-efficient memory expansion rather than HBM-class bandwidth.
CXL 記憶體將此層級進一步擴展至數 TB 的容量。其主要目標在於提供可擴展、可共享且具成本效益的記憶體擴充方案，而非追求 HBM 等級的頻寬。
The implication is significant:
其影響深遠：
AI memory architecture is shifting from maximizing a single bandwidth number toward optimizing the entire memory hierarchy.
AI 記憶體架構正從最大化單一頻寬數值，轉向優化整個記憶體層級。
The most latency-sensitive tensors and hot KV cache can remain in SRAM, 3D DRAM, or HBM. Large model weights, persistent KV cache, embeddings, RAG datasets, and relatively colder context data can potentially migrate into HBF or CXL-attached memory.
對延遲最敏感的張量與熱點 KV 快取可保留於 SRAM、3D DRAM 或 HBM 中；大型模型權重、持久性 KV 快取、嵌入向量（embeddings）、RAG 資料集以及相對較冷的上下文資料，則可遷移至 HBF 或透過 CXL 連接的記憶體。
HBM would therefore no longer need to absorb every incremental increase in AI model capacity.
因此，HBM 將不再需要吸收 AI 模型容量的每一次增量增長。
HBF’s Fundamental Concept: Turning NAND into an HBM-Like Device
HBF 的基本概念：將 NAND 轉變為類似 HBM 的裝置
The most important technological change behind HBF is not simply that NAND becomes faster. Instead, the entire NAND system architecture changes.
HBF 背後最重要的技術變革，並非僅僅是讓 NAND 變得更快，而是整個 NAND 系統架構的改變。
A conventional SSD architecture can be simplified as:
傳統的 SSD 架構可簡化為：
CPU/GPU → PCIe/CXL → SSD Controller → NAND Channels → NAND Flash
CPU/GPU → PCIe/CXL → SSD 控制器 → NAND 通道 → NAND 快閃記憶體
Between the processor and NAND are several layers involving the SSD controller, protocol processing, queues, flash translation layers, and NAND interfaces. The SSD therefore remains fundamentally a storage device.
在處理器與 NAND 之間存在多層架構，涉及 SSD 控制器、協定處理、佇列、快閃轉換層（Flash Translation Layer）以及 NAND 介面。因此，SSD 本質上仍為儲存裝置。
HBF moves toward a very different architecture:
HBF 則朝向截然不同的架構發展：
GPU / TPU / XPU → UCIe → HBF PHY / Logic Die → TSV → Stacked NAND
GPU / TPU / XPU → UCIe → HBF PHY / 邏輯晶粒 → TSV → 堆疊式 NAND
NAND is no longer positioned merely as storage behind PCIe. It becomes anear-compute, high-capacity memory tierlocated much closer to the processor.
NAND 不再僅定位為位於 PCIe 後端的儲存裝置，而是轉變為靠近運算單元、具備高容量的記憶體層級，且位置更貼近處理器。
This is the most important physical implication of HBF.
這是 HBF 最重要的實體意涵。
HBM answered the question:
HBM 回答了以下問題：
How can DRAM be moved closer to the GPU?
如何將 DRAM 更靠近 GPU？
HBF attempts to answer another question:
HBF 則試圖回答另一個問題：
Can NAND also be moved closer to the GPU?
NAND 是否也能更靠近 GPU？
If the answer is yes, the memory and packaging architecture surrounding future AI accelerators could change substantially.
若答案為肯定，未來 AI 加速器周圍的記憶體與封裝架構可能會發生重大變革。
First-Generation HBF: Up to 512GB and Approximately 3TB/s
第一代 HBF：容量高達 512GB，頻寬約 3TB/s
The initial HBF specifications already provide a useful indication of where the technology is heading.
初始的 HBF 規格已清楚指出該技術的發展方向。
Information presented around FMS 2026 indicates that the first-generation HBF capacity specification supports up to approximately512GB, with two major NAND stacking configurations:
FMS 2026 所展示的資訊顯示，第一代 HBF 容量規格支援最高約 512GB，並提供兩種主要的 NAND 堆疊配置：
8-high NAND stack8 層高 NAND 堆疊
and與
16-high NAND stack.16 層堆疊的 NAND。
Bandwidth is divided into three performance grades:
頻寬分為三個效能等級：
Grade 1 → Grade 2 → Grade 3
第 1 級 → 第 2 級 → 第 3 級
with aggregate package bandwidth ranging from roughly0.4TB/s to as high as 3.0TB/s.
整體封裝頻寬範圍從大約 0.4TB/s 到高達 3.0TB/s。
這一點至關重要，因為傳統 NAND 的效能通常是以每個通道的介面速度、NAND 通道數量、IOPS 以及順序 SSD 讀取/寫入效能來討論。
然而，HBF 越來越直接以封裝層級的 TB/s 頻寬來描述。
That alone demonstrates how different its design philosophy is from conventional SSDs.
僅此一點就足以證明，其設計理念與傳統 SSD 截然不同。
Modern NAND interfaces have already reached multi-Gb/s data rates per I/O channel. When a large number of NAND dies and channels are combined through massive parallelism, 3D stacking, a dedicated logic die, and high-speed die-to-die interfaces, the aggregate bandwidth available from a single HBF package can increase dramatically.
現代 NAND 介面的每個 I/O 通道資料傳輸速率已達到多 Gb/s。當透過大規模並行處理、3D 堆疊、專用邏輯晶片以及高速晶片間介面，將大量 NAND 晶粒與通道整合時，單一 HBF 封裝所能提供的總頻寬便可大幅提升。
Therefore, HBF should not be interpreted as:
因此，HBF 不應被解讀為：
“Making one NAND die as fast as DRAM.”
「讓單一 NAND 晶粒的速度媲美 DRAM。」
The more accurate interpretation is:
更準確的解讀是：
“Using massive parallelism to make the aggregate bandwidth of many NAND dies approach the range required by AI memory systems.”
「透過大規模平行處理，使眾多 NAND 晶粒的聚合頻寬達到 AI 記憶體系統所需的範圍。」
This philosophy is actually similar to GPU computing itself. A single execution unit does not need extraordinary performance if thousands of units can operate in parallel and collectively produce enormous throughput.
此理念實際上與 GPU 運算本身相似。若數千個執行單元能平行運作並共同產生巨大的吞吐量，則單一執行單元無需具備非凡的性能。
UCIe Could Become a Critical Enabler for HBF
UCIe 可能成為 HBF 的關鍵推動者
Another important element of the initial HBF architecture is the use ofUCIeas an interconnect between the HBF package and processors.
初始 HBF 架構的另一個重要元素，是採用 UCIe 作為 HBF 封裝與處理器之間的互連介面。
This means that HBF should not be viewed purely as a NAND technology. It is increasingly becoming part of the broader chiplet ecosystem.
這意味著不應將 HBF 單純視為 NAND 技術；它正日益成為更廣泛的 Chiplet 生態系的一部分。
Future architectures could potentially resemble:
未來的架構可能呈現如下形式：
GPU / AI ASIC → UCIe → HBF
or even:甚至：
GPU Compute Die + HBM + HBF + I/O Die
GPU 運算晶粒 + HBM + HBF + I/O 晶粒
integrated within the same package or computing platform.
整合於同一封裝或運算平台內。
This differs fundamentally from the traditional architecture:
這與傳統架構有根本上的差異：
GPU → PCIe → NVMe SSD
With PCIe SSDs, the GPU effectively retrieves data from an external storage device.
透過 PCIe SSD，GPU 實際上可從外部儲存裝置擷取資料。
With UCIe-attached HBF, the long-term objective is to move flash much closer to the compute package and treat it increasingly like a memory resource rather than conventional storage.
透過 UCIe 連接的 HBF，其長期目標是將快閃記憶體更靠近運算封裝，並將其視為愈來愈像記憶體資源，而非傳統儲存裝置。
If successful, future AI systems may no longer need to solve the Memory Wall simply by adding more HBM stacks. Instead, system designers could optimize around heterogeneousHBM + HBF memory architectures.
若成功實現，未來的 AI 系統或許不再需要單純依靠增加更多 HBM 堆疊來解決「記憶體牆」問題。相反地，系統設計者可針對異質性的 HBM + HBF 記憶體架構進行最佳化。
Why Could 4TB of HBF with Four GPUs Approach the Throughput of Eight GPUs with HBM?
為何搭載 4TB HBF 的四顆 GPU，其吞吐量能接近配備 HBM 的八顆 GPU？
One of the most interesting demonstrations at FMS came from Sandisk CTO Alper Ilkbahar.
在 FMS 展會中，最引人注目的展示之一來自 Sandisk 技術長 Alper Ilkbahar。
Sandisk compared two configurations:
SanDisk 比較了兩種組態：
4TB HBF-only + 4 GPUs
4TB 純 HBF + 4 顆 GPU
versus相較於
192GB HBM + 8 GPUs
192GB HBM + 8 顆 GPU
and showed that the two systems could deliver nearly the same token-generation throughput under the modeled workload, effectively suggesting approximately2× higher GPU efficiencyfor the HBF-based configuration.
並顯示兩套系統在模擬工作負載下可提供近乎相同的 token 生成吞吐量，這有效表明基於 HBF 的組態具備約 2 倍更高的 GPU 效率。
This doesnotmean that HBF has already surpassed HBM in either latency or raw bandwidth.
這並不意味著 HBF 在延遲或原始頻寬方面已經超越 HBM。
The real issue is that AI inference workloads are not always compute-bound. They can increasingly becomememory-capacity-bound and memory-movement-bound.
真正的問題在於，AI 推論工作負載並非總是受限於運算能力；它們日益受到記憶體容量與記憶體資料搬移的限制。
Consider a very large model that cannot fit within the HBM capacity available to a small number of GPUs. The model may need to be partitioned across eight GPUs simply because each GPU has insufficient local memory.
請考慮一個規模極大的模型，其大小超過了少數幾顆 GPU 所能提供的 HBM 容量。由於每顆 GPU 的本地記憶體不足，該模型可能需要分割並分散到八顆 GPU 上運行。
This creates additional overhead from GPU-to-GPU communication, synchronization, network fabric utilization, and repeated data movement.
這會因 GPU 之間的通訊、同步、網路架構使用以及重複的資料移動而產生額外的開銷。
If HBF allows each GPU to access hundreds of gigabytes or even terabytes of near-compute memory, the same model might fit across only four GPUs.
如果 HBF 讓每個 GPU 都能存取數百 GB 甚至數 TB 的近端運算記憶體，同樣的模型可能只需四顆 GPU 即可容納。
The real relationship therefore is not:
因此，真正的關係並非：
HBF bandwidth > HBM bandwidth
HBF 頻寬 > HBM 頻寬
but rather:而是：
Larger near-compute memory capacity → fewer GPUs required → less inter-GPU data movement → higher GPU utilization → lower cost per token
更大的近運算記憶體容量 → 所需 GPU 數量減少 → GPU 間資料移動降低 → GPU 利用率提升 → 每 token 成本下降
This is the core idea behind thetoken economicsargument for HBF.
這正是 HBF 代幣經濟論點的核心概念。
HBF Is More Likely to Complement HBM Than Replace It
HBF 更可能作為 HBM 的互補，而非取代它
It would therefore be an oversimplification to interpret HBF as “NAND replacing HBM.”
因此，將 HBF 解讀為「NAND 取代 HBM」過於簡化。
A more realistic future AI memory architecture could look like:
更切合實際的未來 AI 記憶體架構可能如下所示：
SRAM → 3D DRAM → HBM → HBF → CXL Memory → SSD
Different datasets would be placed at different levels according to their requirements for latency, bandwidth, capacity, persistence, and cost.
不同的資料集會根據其對延遲、頻寬、容量、持久性及成本的需求，被放置於不同的層級。
The most latency-sensitive tensor operations and hot KV cache could remain in HBM. Large model weights, persistent KV cache, embeddings, RAG data, and colder context data could potentially reside in HBF.
對延遲最敏感的張量運算與熱鍵值（KV）快取可繼續保留在 HBM 中；大型模型權重、持久性 KV 快取、嵌入向量（embeddings）、檢索增強生成（RAG）資料，以及較冷的上下文資料，則可能存放於 HBF。
This would reduce the amount of HBM required purely for capacity purposes.
如此可降低純粹因容量需求而必須配置的 HBM 用量。
The real value proposition of HBF is therefore not necessarily to eliminate HBM.
因此，HBF 的真正價值主張未必在於取代 HBM。
It is to:其目的在於：
reduce the AI system’s dependence on HBM capacity.
降低 AI 系統對 HBM 容量的依賴。
That distinction has major implications for the broader AI hardware supply chain.
此區別對更廣泛的 AI 硬體供應鏈具有重大影響。
2027–2028 Could Be the Critical Commercialization Window
2027 至 2028 年可能是關鍵的商業化窗口期。
HBF is still in the early stages of development rather than mature mass production.
HBF 仍處於早期開發階段，尚未進入成熟的大規模量產。
The roadmap presented around FMS 2026 indicates that the industry is currently working through the specification and ecosystem-building stage. A more complete HBF specification is expected to emerge in2027, followed by initial product sampling aroundearly 2028, before the technology progresses toward broader commercialization and mass production.
FMS 2026 前後提出的路線圖顯示，產業目前正處於規格制定與生態系建構階段。更完整的 HBF 規格預計於 2027 年問世，隨後在 2028 年初進行首批產品取樣，之後該技術將逐步邁向大規模商業化與量產。
Therefore, the 2026–2027 period should primarily be viewed as the development phase for:
因此，2026 至 2027 年期間應主要被視為以下項目的開發階段：
Specification → Ecosystem → Controller/PHY → Packaging → XPU Integration
規格 → 生態系統 → 控制器/PHY → 封裝 → XPU 整合
while 2028 and beyond could mark the beginning of actual commercial deployment.
而 2028 年及以後可能標誌著實際商業部署的開端。
Another important point is that the standard is not being developed by Sandisk alone. Sandisk and SK hynix are major contributors, while companies such as Google and Tenstorrent have also participated in specification validation and ecosystem development.
另一項重點是，該標準並非由 Sandisk 單獨開發。Sandisk 與 SK hynix 為主要貢獻者，同時 Google 和 Tenstorrent 等公司也參與了規格驗證與生態系統發展。
This suggests that HBF is beginning to bring together NAND suppliers, AI accelerator developers, hyperscalers, and the Open Compute ecosystem.
這顯示 HBF 正開始將 NAND 供應商、AI 加速器開發商、超大型資料中心業者以及開放運算（Open Compute）生態系統匯聚一堂。
HBF Could Redefine the Economic Value of NAND
HBF 可能重新定義 NAND 的經濟價值
From a semiconductor-industry perspective, the most important implication of HBF may not be the first generation’s 512GB capacity or 3TB/s bandwidth.
從半導體產業的角度來看，HBF 最重要的影響或許並非第一代產品的 512GB 容量或 3TB/s 頻寬。
The more important question is whetherNAND’s position in the semiconductor value chain is beginning to change.
更關鍵的問題在於，NAND 在半導體價值鏈中的地位是否正開始發生轉變。
Historically, NAND competition has focused heavily on:
歷史上，NAND 的競爭主要聚焦於：
Layer Count, Bit Density, TLC/QLC, Cost per Bit, Yield, and SSD Capacity.
層數、位元密度、TLC/QLC、每單位位元成本、良率，以及 SSD 容量。
This has made NAND one of the semiconductor industry’s most commodity-like markets.
這使得 NAND 成為半導體產業中最具商品化特性的市場之一。
HBF introduces an entirely new set of competitive dimensions:
HBF 引入了全新的競爭維度：
TSV, Wafer Bonding, Logic Die, PHY, UCIe, Advanced Packaging, Thermal Management, Warpage Control, Stacking Yield, and Controller Architecture.
TSV、晶圓接合、邏輯晶片、PHY、UCIe、先進封裝、熱管理、翹曲控制、堆疊良率與控制器架構。
For example, HBF architectures may require highly optimized NAND dies, advanced wafer bonding, extremely low die warpage for tall stacks, dedicated logic dies, and sophisticated package-level thermal and signal-integrity engineering.
例如，HBF 架構可能需要高度優化的 NAND 晶粒、先進的晶圓接合技術、針對高堆疊結構的極低晶粒翹曲控制、專用的邏輯晶粒，以及複雜的封裝層級熱能與訊號完整性工程。
Future NAND competition may therefore become less about:
因此，未來的 NAND 競爭焦點可能不再在於：
“Who can manufacture the cheapest bit?”
「誰能製造出成本最低的位元？」
and increasingly about:而且越來越聚焦於：
“Who can turn NAND into AI memory?”
「誰能將 NAND 轉化為 AI 記憶體？」
That represents a fundamentally different value proposition.
這代表了一種根本不同的價值主張。
From the HBM Shortage to the AI Memory Hierarchy
從 HBM 短缺到 AI 記憶體階層架構
HBF should therefore not be understood merely as an alternative created because HBM is in short supply.
因此，HBF 不應被單純理解為因 HBM 供不應求而產生的替代方案。
HBM supply constraints certainly increase the incentive to explore alternative memory architectures, but the deeper structural driver is that AI model capacity is growing faster than can economically be solved by simply adding more HBM.
HBM 的供應限制確實提高了探索替代記憶體架構的誘因，但更深层的結構性驅動因素在於，AI 模型的容量成長速度，已無法單純透過增加更多 HBM 來以符合經濟效益的方式解決。
Future AI systems must simultaneously optimize:
未來的 AI 系統必須同時優化：
Compute, Bandwidth, Capacity, Latency, Power, and Cost.
運算、頻寬、容量、延遲、功耗與成本。
This is why the emergence of new memory tiers such as G0.5, G1.5, and G2.5 is so important.
這正是 G0.5、G1.5 與 G2.5 等新記憶體層級出現如此重要的原因。
G0.5 3D-stacked DRAM attempts to fill the performance gap between SRAM and conventional HBM.
G0.5 3D 堆疊 DRAM 旨在填補 SRAM 與傳統 HBM 之間的效能落差。
G1.5 HBF attempts to fill the enormous capacity and cost gap between HBM and lower-tier memory/storage.
G1.5 HBF 旨在填補 HBM 與低階記憶體／儲存裝置之間巨大的容量與成本落差。
G2.5 CXL pooled memory extends capacity even further, providing multi-terabyte memory pools optimized for scalability and cost efficiency.
G2.5 CXL 匯聚式記憶體進一步擴充容量，提供針對可擴展性與成本效益優化的 TB 級記憶體池。
In other words, the next phase of AI server competition may no longer be simply:
換言之，下一階段 AI 伺服器的競爭可能不再單純是：
Who has more HBM?誰擁有更多的 HBM？
Instead, the question may become:
相反地，問題可能會變成：
Who can build the most efficient AI memory hierarchy?
誰能建構出最高效的 AI 記憶體階層？
If HBF eventually succeeds in bringing hundreds of gigabytes, 1TB, or even multiple terabytes of NAND physically and logically closer to GPUs while delivering TB/s-class aggregate bandwidth, the design philosophy of AI accelerators could change significantly.
若 HBF 最終成功將數百 GB、1TB，甚至數 TB 容量的 NAND，在實體與邏輯層面上更貼近 GPU，同時提供 TB/s 等級的聚合頻寬，AI 加速器的設計哲學可能會發生顯著轉變。
GPU count would no longer need to scale as directly with model capacity. HBM would no longer need to accommodate every model weight and every byte of KV cache. Flash would no longer exist solely as an SSD sitting behind a PCIe bus several architectural layers away from the processor.
GPU 數量將不再需要隨著模型容量直接擴增。HBM 也不再需要容納所有的模型權重與每一位元組的 KV 快取。Flash 也將不再僅是位於 PCIe 匯流排後方、與處理器相隔數個架構層級的 SSD。
For the first time, NAND could begin a meaningful transition from a storage device toward compute-adjacent memory.
NAND 首次可能開始從儲存裝置有意義地轉型為鄰近運算的記憶體。
That may ultimately be the most important implication of HBF.
這或許最終是 HBF 最重要的影響。
The real HBF revolution is not simply the creation of a “cheaper alternative to HBM.” It is the potential redefinition ofwhat constitutes memory, what constitutes storage, and where the boundary between the two should exist inside an AI system.
真正的 HBF 革命不僅僅是創造一種「更便宜的 HBM 替代方案」，而是可能重新定義何謂記憶體、何謂儲存，以及兩者在 AI 系統內的界線應位於何處。
As NAND becomes more HBM-like, DRAM becomes increasingly three-dimensional, and CXL enables memory pooling, the next major battle in AI infrastructure may be shifting from pure GPU compute toward a much broaderMemory Architecture War.
隨著 NAND 變得愈來愈像 HBM、DRAM 日益朝向三維化發展，加上 CXL 實現了記憶體池化，AI 基礎設施的下一場重大戰役，可能將從純粹的 GPU 運算，轉向更為廣泛的「記憶體架構之戰」。
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