AMD’s AI Architecture Evolution: From EPYC and Instinct to Helios and Heterogeneous Integration
AMD’s AI Architecture Evolution: From EPYC and Instinct to Helios and Heterogeneous Integration¶
- Source: SemiVision
- Author: SEMIVISION
- Published: 2026-08-24T07:59:00+08:00
- URL: https://tspasemiconductor.substack.com/p/amds-ai-architecture-evolution-from
中文翻譯與英文原文（雙語）¶
(2) AMD 的 AI 架構演進：從 EPYC 與 Instinct 到 Helios 及異質整合 --- (2) AMD’s AI Architecture Evolution: From EPYC and Instinct to Helios and Heterogeneous Integration
AMD’s AI Architecture Evolution: From EPYC and Instinct to Helios and Heterogeneous Integration¶
AMD 的 AI 架構演進：從 EPYC 與 Instinct 到 Helios 及異質整合
Original Article By SemiVision Research [Reading time: 11 mins]¶
原文作者：SemiVision Research [閱讀時間：11 分鐘]
Aug 24, 2026
∙ Paid∙ 付費
Share分享
AMD’s AI Architecture Evolution: From EPYC and Instinct to Helios and Heterogeneous Integration
AMD 的 AI 架構演進：從 EPYC 與 Instinct 到 Helios 及異質整合
AMD’s data center strategy is evolving from traditional CPU- and GPU-centric chip competition toward a comprehensive AI computing platform. Across next-generation EPYC processors, Instinct GPUs, chiplets, SoIC/CoWoS advanced packaging, the Helios rack-scale architecture, custom ASICs, and CPO, a common technology direction is emerging:reducing the cost of data movement through heterogeneous integration while expanding the scope of competition from the chip level to the package, node, rack, and ultimately the entire AI cluster.
AMD 的資料中心策略正從傳統以 CPU 和 GPU 為核心的晶片競爭，演進為全面的 AI 運算平台。透過下一代 EPYC 處理器、Instinct GPU、Chiplet 技術、SoIC/CoWoS 先進封裝、Helios 機架級架構、客製化 ASIC 以及 CPO，一個共同的技術方向逐漸浮現：藉由異質整合降低數據移動成本，同時將競爭範疇從晶片層級擴展至封裝、節點、機架，乃至整個 AI 叢集。
We will share the following topics
我們將分享以下主題
-
Custom ASICs: Extending AMD Beyond General-Purpose CPUs and GPUs
-
客製化 ASIC：將 AMD 的能力從通用 CPU 與 GPU 進一步延伸
-
EPYC’s Core Advantage Is Shifting from Core Count to Chiplet Architecture
-
EPYC 的核心優勢正從核心數量轉向小晶片（Chiplet）架構
-
Memory and I/O Are Becoming the Next EPYC Bottlenecks
-
記憶體與 I/O 正成為下一代 EPYC 的瓶頸
-
CPU and GPU Architectures Are Moving from External Connectivity Toward Platform-Level Integration
-
CPU 與 GPU 架構正從外部連接轉向平台層級整合
-
Helios: AMD’s Transition from a Chip Company to Rack-Scale Computing
-
Helios：AMD 從晶片公司轉型為機架規模運算
-
Instinct GPUs: Moving from Process Scaling to Advanced Packaging Scaling
-
Instinct GPU：從製程微縮轉向先進封裝微縮
-
SoIC and CoWoS: Two Different Dimensions of GPU Scaling
-
SoIC 與 CoWoS：GPU 擴展的兩個不同維度
-
Advanced Packaging Competition Is Shifting from Capacity Toward Yield
-
先進封裝競爭正從產能轉向良率
-
The Next Generation of Instinct: System Scaling Matters More Than Standalone GPU Performance
-
下一代 Instinct：系統擴展性比單一 GPU 效能更為重要
-
CPO: Addressing the Next Electrical I/O Bottleneck
-
CPO：解決下一個電氣 I/O 瓶頸
-
AMD’s Technology Roadmap Is Fundamentally About Solving Data Movement
-
AMD 的技術路線圖核心在於解決資料移動問題
-
Custom ASICs: Extending AMD Beyond General-Purpose CPUs and GPUs
-
客製化 ASIC：將 AMD 的能力從通用 CPU 與 GPU 進一步延伸
One of AMD’s most important future opportunities is extending its existing CPU, GPU, and chiplet capabilities into custom ASICs.
AMD 未來最重要的機會之一，是將其現有的 CPU、GPU 及小晶片（chiplet）能力延伸至客製化 ASIC 領域。
Large cloud service providers are increasingly adopting two parallel AI computing architectures. One relies on general-purpose accelerators such as GPUs, while the other uses internally developed ASICs optimized for specific AI workloads. These two approaches are not necessarily substitutes and could coexist within large-scale data centers.
大型雲端服務供應商正日益採用兩種並行的 AI 運算架構。一種依賴如 GPU 等通用加速器，另一種則使用針對特定 AI 工作負載最佳化的內部自研 ASIC。這兩種方法並非必然互斥，而是可以在大規模資料中心內共存。
AMD’s key competitive advantage in this market is not simply ASIC design capability, but its long-standing expertise inheterogeneous computing integration.
AMD 在該市場的關鍵競爭優勢，並非僅在於 ASIC 設計能力，更在於其長期累積的異質運算整合專業技術。
AMD has already established a modular architecture consisting of CPU compute dies, GPU compute dies, I/O dies, HBM, Infinity Fabric, and chiplet packaging. If AMD participates in future CSP custom ASIC programs, its role could extend beyond designing an individual accelerator to integrating customer-owned accelerator IP with AMD’s CPU, I/O, memory controller, die-to-die interconnect, and packaging technologies.
AMD 已建立一套模組化架構，包含 CPU 運算晶粒、GPU 運算晶粒、I/O 晶粒、HBM、Infinity Fabric 互連技術以及小晶片（chiplet）封裝。若 AMD 參與未來雲端服務供應商（CSP）的客製化 ASIC 專案，其角色將不僅限於設計單一加速器，更可擴展至將客戶自有的加速器 IP 與 AMD 的 CPU、I/O、記憶體控制器、晶粒對晶粒（die-to-die）互連技術及先進封裝進行深度整合。
The primary technical benefit of this architecture is reduced data movement.
此架構的主要技術效益在於降低資料移動成本。
When CPUs and accelerators exchange large amounts of data through conventional PCIe interfaces and PCB-level connections, the system incurs additional SerDes power consumption, signal loss, and latency. Moving these computing elements closer together through chiplets and advanced packaging can significantly increase bandwidth density while reducing energy consumption per bit.
當 CPU 與加速器透過傳統 PCIe 介面及 PCB 層級連接交換大量資料時，系統將產生額外的 SerDes 功耗、訊號損耗與延遲。藉由小晶片與先進封裝技術將這些運算元件更緊密地整合，可大幅提升頻寬密度，同時降低每位元傳輸的能耗。
From this perspective, custom ASICs represent a natural extension of AMD’s CPU/GPU heterogeneous integration capabilities into third-party accelerator IP.
從這個角度來看，客製化 ASIC 代表了 AMD 將其 CPU/GPU 異質整合能力自然延伸至第三方加速器 IP。
-
EPYC’s Core Advantage Is Shifting from Core Count to Chiplet Architecture
-
EPYC 的核心優勢正從核心數量轉向小晶片（Chiplet）架構
The competitiveness of AMD EPYC should no longer be evaluated solely by CPU core count.
評估 AMD EPYC 的競爭力時，不應再僅以 CPU 核心數量為唯一標準。
Its fundamental advantage comes from a highly modular chiplet architecture that allows the same compute dies to be combined through different configurations, binning strategies, and packaging schemes to create multiple server CPU SKUs.
其根本優勢來自高度模組化的小晶片（chiplet）架構，該架構允許透過不同的組態、分級（binning）策略與封裝方案，將相同的運算晶粒組合起來，從而打造出多款伺服器 CPU 產品型號（SKU）。
The architecture can be simplified as:
該架構可簡化為：
Compute Die → Chiplet → I/O Die → Package → Server Platform
運算晶粒 → 小晶片 → I/O 晶粒 → 封裝 → 伺服器平台
Compute dies provide the primary processing capability, while the I/O die integrates memory controllers, PCIe/CXL, fabric connectivity, and external I/O.
運算晶粒提供主要的處理能力，而 I/O 晶粒則整合記憶體控制器、PCIe/CXL、互連結構連接性以及外部 I/O。
This architecture provides three major advantages over large monolithic CPUs.
此架構相較於大型單片式 CPU 具備三大優勢。
The first is yield. As monolithic die size increases, a single defect can cause the entire chip to be discarded. Chiplets divide the processor into smaller dies, improving wafer utilization and manufacturing economics.
首先是良率。隨著單晶圓尺寸增大，單一缺陷就可能導致整顆晶片報廢。Chiplet 技術將處理器分割為較小的晶粒，從而提升晶圓利用率並改善製造經濟效益。
The second is process optimization. Compute dies can adopt the most advanced logic process, while certain I/O functions do not necessarily require the same leading-edge node. Different functions can therefore be optimized independently for performance, cost, and yield.
其次是製程優化。運算晶粒可採用最先進的邏輯製程，而某些 I/O 功能則未必需要同樣先進的節點。因此，不同功能可針對效能、成本與良率進行獨立優化。
The third is product flexibility. The same compute die can support different core counts, TDPs, and memory configurations, allowing AMD to address multiple server segments with a common silicon platform.
第三是產品靈活性。相同的運算晶粒可支援不同的核心數量、TDP 與記憶體組態，使 AMD 能以共通的矽平台滿足多個伺服器市場區隔的需求。
As a result, the next stage of EPYC competition is no longer simply about adding more cores. The key equation is increasingly:
因此，EPYC 的下一階段競爭已不再單純是增加核心數量。關鍵公式日益趨向於：
Compute Density × Memory Bandwidth × I/O Bandwidth × Packaging Efficiency × Power Efficiency
運算密度 × 記憶體頻寬 × I/O 頻寬 × 封裝效率 × 電源效率
-
Memory and I/O Are Becoming the Next EPYC Bottlenecks
-
記憶體與 I/O 正成為 EPYC 的下一個瓶頸
As CPU core density continues to increase, server processors face a fundamental challenge: if memory bandwidth does not scale accordingly, the incremental benefit of adding more cores begins to decline.
隨著 CPU 核心密度持續提升，伺服器處理器面臨一項根本性挑戰：若記憶體頻寬無法相應擴展，增加更多核心所帶來的遞增效益將開始下降。
因此，未來的 EPYC 升級將不僅聚焦於運算晶片（compute dies），也將日益重視 I/O 晶片。
The I/O die must simultaneously support:
I/O 晶片必須同時支援：
DDR Memory Interfaces, PCIe, CXL, Chiplet Interconnects, Accelerator Connectivity, and Network I/O.
DDR 記憶體介面、PCIe、CXL、小晶片互連（Chiplet Interconnects）、加速器連接以及網路 I/O。
This is transforming the I/O die from a relatively supporting component into one of the most important elements of server CPU architecture.
這正促使 I/O 晶片從相對輔助性的元件，轉變為伺服器 CPU 架構中最關鍵的要素之一。
The change is particularly important in AI servers, where CPUs continuously exchange data with GPUs, NICs, DPUs, storage, CXL memory, and other accelerators. CPU performance therefore increasingly depends on total system I/O throughput rather than core performance alone.
此項變革在 AI 伺服器中尤為關鍵，因為 CPU 必須持續與 GPU、NIC、DPU、儲存裝置、CXL 記憶體及其他加速器進行資料交換。因此，CPU 的效能愈來愈取決於整體系統的 I/O 吞吐量，而非僅靠核心效能。
Server CPU performance should therefore gradually be evaluated not simply as:
因此，伺服器 CPU 的效能評估不應再單純視為：
Core Count × IPC × Frequency
核心數量 × IPC × 頻率
but increasingly as:而應日益著重於：
Compute × Memory × I/O × Interconnect ÷ Power
運算 × 記憶體 × I/O × 互連 ÷ 功耗
-
CPU and GPU Architectures Are Moving from External Connectivity Toward Platform-Level Integration
-
CPU 與 GPU 架構正從外部連接轉向平台層級整合
The relationship between CPUs and GPUs in AI servers is also changing.
AI 伺服器中 CPU 與 GPU 的關係也正在發生變化。
In traditional architectures, the CPU primarily functions as the host processor, while GPUs operate as accelerators attached to the CPU. This creates a relatively clear host-accelerator hierarchy.
在傳統架構中，CPU 主要作為主機處理器運作，而 GPU 則作為附掛於 CPU 的加速器。這形成了一種相對明確的主機 - 加速器層級結構。
However, large AI models generate increasingly demanding workloads involving data preprocessing, memory management, KV cache, networking, storage access, and distributed computing. As a result, CPUs are once again becoming a critical component of AI infrastructure.
然而，大型 AI 模型產生了日益嚴苛的工作負載，涉及資料前處理、記憶體管理、KV 快取、網路、儲存存取以及分散式運算。因此，CPU 再次成為 AI 基礎設施的關鍵元件。
AMD’s future direction is therefore unlikely to focus simply on increasing GPU counts. Instead, the priority will be improving coordination among CPUs, GPUs, and memory.
因此，AMD 未來的發展方向不太可能僅聚焦於增加 GPU 數量。相反地，優先事項將是提升 CPU、GPU 與記憶體之間的協同作業能力。
The architecture is gradually evolving from:
該架構正逐步從以下方向演進：
CPU → PCIe → GPU
toward:朝向：
CPU ↔ High-Speed Fabric ↔ GPU ↔ HBM
CPU ↔ 高速互連架構 ↔ GPU ↔ HBM
and eventually:最終演進為：
CPU + GPU + HBM + NIC + Switch + Optical I/O
CPU + GPU + HBM + NIC + Switch + 光學 I/O
This is also one of the fundamental architectural principles behind Helios.
這亦是 Helios 背後的根本架構原則之一。
-
Helios: AMD’s Transition from a Chip Company to Rack-Scale Computing
-
Helios：AMD 從晶片公司轉型為機架規模運算
The significance of Helios extends well beyond the introduction of a new rack platform. It represents AMD’s effort to expand the design boundary of AI systems from the package level to the rack level.
Helios 的意義遠不止於推出新的機架平台，它代表了 AMD 致力於將 AI 系統的設計邊界從封裝層級擴展至機架層級。
Historically, AMD primarily supplied EPYC CPUs and Instinct GPUs, while server OEMs and ODMs integrated those components into complete systems.
歷史上，AMD 主要供應 EPYC CPU 與 Instinct GPU，而伺服器 OEM 與 ODM 廠商則負責將這些元件整合為完整系統。
A rack-scale architecture requires AMD to participate in the co-design of:
機架級架構要求 AMD 參與以下項目的共同設計：
CPU, GPU, HBM, Interconnect, Switches, NICs, Power Delivery, Liquid Cooling, Mechanical Architecture, and Software.
CPU、GPU、HBM、互連技術、交換器、NIC、電源供應、液冷散熱、機械架構與軟體。
The fundamental unit of AI hardware design is therefore evolving:
因此，AI 硬體設計的基本單位正持續演進：
Die → Package → Board → Tray → Rack → Cluster
晶粒 → 封裝 → 電路板 → 托盤 → 機架 → 叢集
A GPU is no longer an isolated product. It becomes one compute element within a much larger AI factory.
GPU 已不再是孤立的產品，而是成為大型 AI 工廠中的一個運算元件。
This reflects the broader direction of AI infrastructure. As individual accelerators become more powerful and consume more power, system performance is increasingly constrained by memory bandwidth, network bandwidth, power delivery, cooling capacity, and interconnect efficiency.
這反映了 AI 基礎設施的整體發展方向。隨著單一加速器的效能日益提升且功耗不斷增加，系統效能越來越受到記憶體頻寬、網路頻寬、電力供應、散熱能力以及互連效率的限制。
AMD’s competitiveness therefore needs to be evaluated increasingly at the rack level rather than solely through GPU FLOPS.
因此，評估 AMD 的競爭力時，應日益著重於機櫃層級，而非僅限於 GPU 的 FLOPS。
-
Instinct GPUs: Moving from Process Scaling to Advanced Packaging Scaling
-
Instinct GPU：從製程微縮轉向先進封裝微縮
Another major transition in next-generation Instinct GPUs is that semiconductor process scaling alone is no longer sufficient to sustain AI performance growth.
下一代 Instinct GPU 的另一項重大轉變在於，僅靠半導體製程微縮已不足以維持 AI 效能的成長。
GPU architectures are increasingly moving from a single large die toward:
GPU 架構正日益從單一大型晶粒轉向：
Multiple Compute Dies + I/O Dies + HBM + Advanced Packaging
多個運算晶粒 + I/O 晶粒 + HBM + 先進封裝
Advanced packaging is therefore becoming part of the GPU architecture itself rather than simply a back-end manufacturing process.
因此，先進封裝已成為 GPU 架構本身的一部分，而不僅僅是後段製造製程。
AMD can divide different functions across multiple dies and reconnect them through high-speed die-to-die interfaces to create a much larger accelerator.
AMD 可將不同功能分散至多個晶粒（die），並透過高速晶粒對晶粒介面將其重新連接，以建構規模更大的加速器。
This architecture reduces the yield risk associated with extremely large monolithic dies while allowing different functional blocks to use different process technologies.
此架構降低了與極大尺寸單晶圓晶片相關的良率風險，同時允許不同的功能區塊採用不同的製程技術。
The trade-off is significantly higher packaging complexity.
代價是封裝複雜度顯著提高。
GPU yield can therefore no longer be evaluated solely through front-end wafer yield. The relevant equation increasingly becomes:
因此，GPU 良率已無法再僅透過前端晶圓良率來評估。相關的計算公式日益變為：
KGD Yield × Bonding Yield × Interconnect Yield × HBM Yield × Packaging Yield × Final Test Yield
KGD 良率 × 接合良率 × 互連良率 × HBM 良率 × 封裝良率 × 最終測試良率
A problem at any stage can reduce the number of final shippable accelerators.
任何階段出現問題，都可能減少最終可出貨的加速器數量。
-
SoIC and CoWoS: Two Different Dimensions of GPU Scaling
-
SoIC 與 CoWoS：GPU 擴展的兩個不同維度
Within advanced packaging, SoIC and CoWoS can be viewed as addressing two different dimensions of scaling.
在先進封裝領域中，SoIC 與 CoWoS 可視為分別針對縮放（scaling）的兩個不同面向提供解決方案。
SoIC primarily addresses Z-axis, or vertical, scaling.
SoIC 主要解決 Z 軸（垂直）擴展問題。
Through 3D stacking and hybrid bonding, different dies can be connected with much higher interconnect density, reducing die-to-die distance, increasing bandwidth density, and lowering communication power.
透過 3D 堆疊與混合鍵合技術，不同晶粒得以以更高的互連密度連接，縮短晶粒間距離、提升頻寬密度，並降低通訊功耗。
CoWoS primarily addresses X-Y, or horizontal, scaling.
CoWoS 主要解決 X-Y 軸（水平）擴展問題。
Through interposers, RDL, and advanced substrates, GPU compute dies, I/O dies, and multiple HBM stacks can be integrated into a large package.
藉由中介層、重佈線層（RDL）及先進基板技術，可將 GPU 運算晶粒、I/O 晶粒以及多個 HBM 堆疊整合於單一大型封裝中。
The architectural relationship can therefore be simplified as:
因此，架構關係可簡化為：
SoIC = Vertical Integration
SoIC = 垂直整合
CoWoS = Horizontal Integration
CoWoS = 水平整合
Together, these technologies allow accelerators to move beyond the physical limitations of a single reticle, a single die, and eventually a conventional package.
這些技術共同使加速器得以突破單一光罩、單一晶粒，乃至傳統封裝的物理限制。
-
Advanced Packaging Competition Is Shifting from Capacity Toward Yield
-
先進封裝競爭正從產能轉向良率
As AI GPU packages become larger and more complex, comparing CoWoS capacity alone is no longer sufficient to determine actual supply capability.
隨著 AI GPU 封裝變得更大且更複雜，僅比較 CoWoS 產能已不足以判斷實際的供應能力。
The more important metric isGood Package Output.
更重要的指標是良率封裝產出量（Good Package Output）。
A large AI accelerator can simultaneously contain multiple logic dies, multiple HBM stacks, interposers or RDL structures, advanced substrates, and a large number of micro-bump or hybrid-bonding interfaces.
大型 AI 加速器可同時包含多個邏輯晶粒、多個 HBM 堆疊、中介層或 RDL 結構、先進基板，以及大量的微凸塊或混合鍵結介面。
A defect in any critical die or interface can significantly reduce package yield and create substantial economic losses.
任何關鍵晶粒或介面的缺陷都可能大幅降低封裝良率，並造成重大的經濟損失。
The competitiveness of advanced packaging will therefore increasingly be determined by four capabilities:
因此，先進封裝的競爭力將日益取決於四項關鍵能力：
Capacity + Yield + Integration + Test
產能＋良率＋整合＋測試
This is also why suppliers capable of coordinating wafer fabrication, advanced packaging, 3D integration, and testing are becoming increasingly important within the AI accelerator supply chain.
這也正是為何在 AI 加速器供應鏈中，能夠協調晶圓製造、先進封裝、3D 整合與測試的供應商變得愈發重要。
-
The Next Generation of Instinct: System Scaling Matters More Than Standalone GPU Performance
-
下一代 Instinct：系統擴展性比單一 GPU 效能更為重要
Performance improvements in next-generation GPUs should not simply be interpreted as one GPU delivering a certain multiple of its predecessor’s performance.
下一代 GPU 的性能提升，不應單純解讀為單一 GPU 提供其前代產品性能的某個倍數。
AI training and inference performance are increasingly dependent on the entire system architecture.
AI 訓練與推論效能日益取決於整體系統架構。
Effective performance is determined by:
有效效能取決於：
Compute Performance運算效能
HBM BandwidthHBM 頻寬
Scale-Up BandwidthScale-Up 頻寬
Scale-Out Networking擴展網路
Software Efficiency軟體效率
Cluster Utilization叢集利用率
Even if standalone GPU compute performance rises significantly, insufficient communication bandwidth between GPUs can still constrain overall cluster performance.
即使獨立 GPU 的運算效能顯著提升，若 GPU 之間的通訊頻寬不足，仍會限制整體叢集的效能。
This is why the competitive focus of future Instinct generations will increasingly extend beyond GPU silicon toward the broader Helios platform.
這就是為什麼未來 Instinct 世代的競爭焦點將日益從 GPU 矽晶本身，擴展至更廣泛的 Helios 平台。
The actual product is no longer simply a:
實際產品已不再單純是：
GPU
but rather a:而是：
GPU ClusterGPU 叢集
and ultimately an:並最終成為：
AI FactoryAI 工廠
-
CPO: Addressing the Next Electrical I/O Bottleneck
-
CPO：解決下一個電氣 I/O 瓶頸
As GPU clusters continue to scale, networking becomes the next major system bottleneck.
隨著 GPU 叢集持續擴展，網路成為下一個主要的系統瓶頸。
With each generation of higher-speed SerDes, PCB traces, connectors, package routing, and retimers face rapidly increasing challenges in insertion loss, power consumption, and signal integrity.
隨著每一代更高速的 SerDes 問世，PCB 走線、連接器、封裝佈線以及重定時器（retimer）在插入損耗、功耗和訊號完整性方面面臨日益嚴峻的挑戰。
The traditional architecture:
傳統架構：
Switch ASIC → Package → PCB → Connector → Optical Module
交換器 ASIC → 封裝 → PCB → 連接器 → 光學模組
therefore faces increasing difficulty as high-speed electrical channels become longer and more lossy.
因此，隨著高速電氣通道變得更長且損耗更高，其面臨的挑戰也日益嚴峻。
CPO changes this architecture toward:
CPO 將此架構轉變為：
Switch ASIC → Optical Engine → Fiber
Switch ASIC → 光學引擎 → 光纖
By moving the optical engine much closer to the switch ASIC, the length of the high-speed electrical path can be substantially reduced.
透過將光學引擎更靠近 Switch ASIC，可大幅縮短高速電氣路徑的長度。
This can reduce:這可以減少：
Insertion Loss, SerDes Power, Retimer Requirements, and PCB Signal Integrity Pressure.
插入損耗、SerDes 功耗、Retimer 需求，以及 PCB 訊號完整性壓力。
CPO should therefore not simply be viewed as moving an optical transceiver into the package. It represents a broader redesign of the AI cluster I/O architecture.
因此，CPO 不應僅被視為將光學收發器移至封裝內；它代表著對 AI 叢集 I/O 架構更廣泛的重新設計。
-
AMD’s Technology Roadmap Is Fundamentally About Solving Data Movement
-
AMD 的技術路線圖核心在於解決資料移動問題
When EPYC, Instinct, SoIC, CoWoS, Helios, and CPO are viewed together, AMD’s technology strategy can be understood as addressing one fundamental challenge:
當我們將 EPYC、Instinct、SoIC、CoWoS、Helios 與 CPO 綜合來看時，便能理解 AMD 的技術策略旨在解決一個根本挑戰：
Data Movement.資料移動。
CPU chiplets address data movement between compute dies.
CPU 小晶片（chiplets）解決了運算晶粒之間的資料移動問題。
HBM addresses data movement between compute and memory.
HBM 解決了運算與記憶體之間的資料傳輸問題。
SoIC addresses vertical die-to-die data movement.
SoIC 解決垂直晶粒對晶粒的資料移動。
CoWoS addresses package-level data movement between GPUs and HBM.
CoWoS 解決封裝層級中 GPU 與 HBM 之間的資料移動。
High-speed fabrics address CPU-to-GPU and GPU-to-GPU communication.
高速互連架構處理 CPU 對 GPU 以及 GPU 對 GPU 的通訊。
Helios addresses rack-scale compute coordination.
Helios 解決機架規模的運算協調。
CPO ultimately addresses rack-to-rack and cluster-scale data movement.
CPO 最終解決的是機櫃間乃至叢集規模的資料移動問題。
The fundamental bottleneck of AI computing is therefore gradually shifting from insufficient compute capability toward the inability to move data efficiently enough to keep that compute fully utilized.
因此，AI 運算的根本瓶頸正逐漸從運算能力不足，轉向無法有效率地移動資料以充分發揮運算效能。
Conclusion: From Chiplet Scaling to AI Factory Scaling
結論：從晶片小晶粒（Chiplet）擴展到 AI 工廠規模擴展
AMD’s most important architectural breakthrough over the past decade has been chiplets.
AMD 過去十年最重要的架構突破是晶片小塊（chiplets）。
Chiplets allowed AMD to overcome many of the cost and yield limitations associated with increasingly large monolithic processors while establishing a highly modular EPYC architecture.
Chiplet 技術使 AMD 得以克服與日益龐大的單晶圓處理器相關的成本與良率限制，同時建立起高度模組化的 EPYC 架構。
The next stage of competition, however, extends far beyond chiplets.
然而，下一階段的競爭已遠超越 Chiplet 的範疇。
AMD’s scaling roadmap is increasingly evolving through:
AMD 的擴展路線圖正持續演進，其發展路徑如下：
Transistor Scaling → Chiplet Scaling → Package Scaling → Rack Scaling → Cluster Scaling
電晶體擴展 → Chiplet 擴展 → 封裝擴展 → 機架擴展 → 叢集擴展
EPYC addresses CPU compute scaling.
EPYC 解決 CPU 運算擴展問題。
Instinct addresses accelerator scaling.
Instinct 解決加速器擴展問題。
SoIC and CoWoS address package scaling.
SoIC 和 CoWoS 解決封裝擴展問題。
Helios addresses rack scaling.
Helios 解決機架擴展問題。
Networking and CPO extend this architecture into cluster scaling.
網路與共封裝光學（CPO）將此架構延伸至叢集擴展層級。
As a result, AMD’s future competition with NVIDIA, Intel, and hyperscaler-developed ASICs should no longer be understood simply as CPU versus CPU or GPU versus GPU.
因此，AMD 未來與 NVIDIA、Intel 及超大型雲端服務商自研 ASIC 的競爭，不應再被單純理解為 CPU 對 CPU 或 GPU 對 GPU 的較量。
The real competition is increasingly aboutwhich architecture can deploy the greatest amount of useful AI compute within a rack—and eventually across an entire data center—while minimizing power consumption, latency, and data movement costs.
真正的競爭日益取決於哪種架構能在單一機櫃內（並最終擴展至整個資料中心）部署最大量的有效 AI 運算能力，同時將功耗、延遲與數據移動成本降至最低。
From this perspective, AMD’s most important long-term technology asset is not any individual CPU or GPU. It is the integrated heterogeneous computing platform formed by:
從這個觀點來看，AMD 最重要的長期技術資產並非任何單一的 CPU 或 GPU，而是由以下要素所構成的整合式異質運算平台：
EPYC + Instinct + Chiplets + HBM + Advanced Packaging + Networking + Helios + CPO
EPYC + Instinct + Chiplets + HBM + 先進封裝 + 網路 + Helios + CPO
AMD’s technology strategy is therefore evolving from“More Compute per Chip”toward a much broader objective:
因此，AMD 的技術策略正從「每顆晶片提供更多運算能力」轉向更廣泛的目標：
“More Useful Compute per AI Factory.”
「每座 AI 工廠提供更多有效運算能力。」
Share分享
Previous上一頁Next下一則