CPC: The AI Rack Cabling Revolution: From PCB Topology to Cable Backplanes
CPC: The AI Rack Cabling Revolution: From PCB Topology to Cable Backplanes¶
- Source: SemiVision
- Author: SEMIVISION
- Published: 2026-07-31T13:44:48+08:00
- URL: https://tspasemiconductor.substack.com/p/cpc-the-ai-rack-cabling-revolution (1) CPC: The AI Rack Cabling Revolution: From PCB Topology to Cable Backplanes
CPC: The AI Rack Cabling Revolution: From PCB Topology to Cable Backplanes¶
Original Article By SemiVision Research [Reading time: 12 mins]¶
Jul 31, 2026
∙ Paid
The Open Compute Project (OCP) is bringing together APAC communities for a very special two-day, in-person Summit to explore the many challenges and opportunities facing data center infrastructure, today and tomorrow. The OCP APAC Summit will showcase the latest innovations and technical advancements from around the world, and feature talks from experts who are researching, designing, building and running the next generation of hyperscale data center facilities and infrastructure. The Expo Hall will bring together buyers and sellers from the entire ecosystem and supply chain.
https://2026ocpapac.fnvirtual.app/
The AI Rack Cabling Revolution: From PCB Topology to Cable Backplanes
In traditional server and switch designs, signal topology is typically built around the PCB. High-speed signals exit the ASIC package, enter the motherboard, traverse multiple layers of PCB routing, and finally connect to front-panel modules or backplanes through connectors. This architecture remained viable in the 56G and 112G SerDes generations, but once data rates enter the 224G PAM4 era, the signal loss in PCB routing begins to deteriorate rapidly.
This is why hyperscalers, when designing next-generation AI cluster architectures, are rethinking the entire rack-level cabling strategy. Instead of relying on traditional PCB backplanes, new designs are gradually shifting toward a cabled backplane architecture. In this approach, connections within the rack are no longer implemented through PCB routing, but rather through high-speed cables directly linking system components.
Co-Packaged Copper (CPC) plays a central role in this architecture. By integrating high-speed connectors directly onto the package substrate, CPC allows cables to extend directly from the chip package to other modules within the rack. This design not only reduces signal loss but also provides significantly greater flexibility in rack-level wiring.
In some AI cluster design scenarios, a rack containing 72 XPUs may require over three kilometers of total copper cable length to complete its internal interconnects. If a CPC cable backplane architecture is used, the system can save tens of kilowatts of power while eliminating the latency and energy overhead introduced by retimer circuits.
This indicates that AI rack design is shifting from a “motherboard-centric” architecture to a “cable-centric” architecture. In this new model, the PCB is no longer the core of the interconnect topology—the cable network itself becomes the structural backbone of the system.
3月6日
Below we will share:
Signal Integrity Advantages of CPC and Flyover Cable
The Interconnect Philosophy of Broadcom vs. NVIDIA
The Formation of the CPC Supply Chain
The Cost Battle Between CPC and Optical Interconnects
CPC and the Timeline of AI Interconnect Evolution
6月1日
Signal Integrity Advantages of CPC and Flyover Cable
To understand why CPC can extend the lifespan of copper interconnects, it is necessary to analyze the problem from the perspective of signal integrity.
In high-speed digital communication, signal degradation primarily comes from three sources:
PCB dielectric loss
Via transition loss
Connector reflection
In traditional PCB routing, signals must pass through multiple vias and long trace paths, which introduce significant reflection and insertion loss.
The CPC architecture uses flyover cables to extract signals directly from the package, allowing them to bypass these high-loss regions. Because twinax cables provide strong shielding and low skew, their insertion loss is significantly lower than that of PCB traces.
In test platforms jointly demonstrated by Broadcom and Samtec, the Si-Fly HD CPC cable system paired with 200G SerDes enabled 512 lanes of 200G connectivity on a single package substrate, delivering a total bandwidth of 102.4 Tbps.
More importantly, the entire link in this channel design can remain fully passive, requiring no retimers or DSP components. This gives CPC a substantial advantage in both power efficiency and latency.
The Interconnect Philosophy of Broadcom vs. NVIDIA
From an industry perspective, the development of CPC also reflects different strategic philosophies in data center interconnect design.
Broadcom has long dominated the Ethernet switch ASIC market, and its strategy focuses on promoting an open and modular data center networking architecture. In this model, switches, servers, and optical modules are interchangeable standard components. CPC fits naturally into this framework—it allows switch ASICs to continue using pluggable optics while reducing channel loss near the package.
The strategy of NVIDIA is fundamentally different. Because NVIDIA controls the GPU, interconnect protocols, and system architecture, it tends to design highly integrated and vertically optimized systems. Technologies such as NVLink and NVSwitch are intended to create a dedicated interconnect fabric within GPU clusters.
In such architectures, NVIDIA tends to rely on custom cables or board-level interconnects rather than standardized Ethernet switching systems. This is why, in some NVIDIA AI rack designs, the scale-up network still relies heavily on copper cables, while optical interconnects are primarily used in the scale-out network.
In essence, the competition between Broadcom and NVIDIA in interconnect architecture can be seen as open networking versus proprietary interconnect fabric. CPC serves as a key tool for Broadcom to extend and strengthen its Ethernet ecosystem.
3月18日
Packaging and Manufacturing Challenges of CPC
Although the concept of CPC appears straightforward, its implementation still involves several packaging and manufacturing challenges.
First is the routing complexity of the package substrate. When hundreds of high-speed channels exit the package, the substrate must simultaneously handle power distribution, signal routing, and mechanical support. This places extremely demanding requirements on substrate design and manufacturing.
Second is the mechanical reliability of the connectors. Because CPC cables connect directly near the package, their insertion and retention mechanisms must remain stable under high temperatures and mechanical vibration.
Thermal management is another key issue. In high-density AI switches, ASIC power consumption can exceed 500 W. If CPC cables and cooling systems are not properly integrated, they may negatively affect the thermal management of the entire package.
Despite these challenges, the manufacturing complexity of CPC is still lower than that of CPO, which must address issues such as optical alignment precision and laser reliability. This is why many industry observers believe CPC represents a more practical near-term deployment path.
CPC in the 448G and 1.6T Interconnect Era
In the coming years, data center interconnects will enter a new performance generation.
Mainstream switching ASICs have already moved into the 112G SerDes generation, with 224G PAM4 as the next major step. Looking further ahead, 448G SerDes and 1.6T ports are also expected to emerge.
In these high-speed generations, CPC will serve as an important transitional technology. By bypassing PCB routing, CPC enables copper interconnects to remain viable in the 224G generation.
Industry consensus suggests that CPC may also provide a practical pathway for 448G SerDes, allowing high-speed electrical interconnects to extend for one more technology generation.
However, as data rates continue to increase, optical interconnects will gradually take over more applications, particularly in communications between racks and across data centers, where fiber offers irreplaceable advantages.
The Hybrid Interconnect Architecture of Future AI Data Centers
Based on current technological trends, future AI data centers will likely adopt a multi-layered interconnect architecture.
Within chips and packages, high-speed electrical interconnects will remain the most efficient solution.
Within racks, CPC and DAC cables will continue to dominate the scale-up network.
Between racks and across clusters, optical interconnects will gradually become the mainstream technology.
In other words, the interconnect technology of future data centers will not be dominated by a single solution. Instead, it will evolve into a hybrid architecture where copper and optics coexist for the long term.
CPC as a Critical Bridge in AI Interconnect Evolution
Data center interconnects in the AI era are currently undergoing a critical transition phase. As compute demand continues to grow, traditional PCB-based electrical interconnects are approaching their physical limits, while optical technologies still face challenges in cost, manufacturing, and ecosystem maturity.
The emergence of Co-Packaged Copper provides a practical pathway through this transition. By innovating in package and cable architectures, CPC extends the lifespan of copper interconnects in high-speed generations while simultaneously paving the way for future optical architectures.
Over the next decade, CPC is likely to become one of the core technologies in scale-up networks for AI data centers. It represents both a continuation of copper interconnect technology and an essential bridge toward the optical interconnect era.
The Physical Reality of AI Rack Cabling: A Jungle of Copper Cables
As AI data centers scale to tens of thousands or even hundreds of thousands of GPUs, rack-level cabling has become one of the most challenging engineering problems. Public images of AI systems often show neat rows of server racks, but the reality inside these racks is far more complex. In large AI training systems, GPUs must continuously exchange gradients and model parameters, meaning that GPU-to-GPU interconnect density far exceeds that of traditional data centers.
In some AI rack designs, a single rack may contain more than a thousand high-speed interconnect links. These links must not only deliver extremely high bandwidth but also maintain ultra-low latency. When each link operates at 200 Gb/s or higher, the inside of a rack effectively becomes a dense network of copper cables.
In AI systems designed by companies such as NVIDIA, NVLink cables provide a clear example. At 200 Gb/s per lane, the diameter, weight, and management complexity of copper cables increase rapidly, making rack-level wiring extremely difficult. Research indicates that at these speeds, cable management can even impact thermal performance and signal integrity.
As a result, AI rack designers face a fundamental challenge:
How can the industry retain the low-power advantages of copper interconnects while preventing the explosion of cable complexity inside the rack?
CPCemerged precisely in response to this challenge.
CPC does not simply add more copper cables; instead, it redesigns the entire signal escape path. By routing high-speed I/O directly from the package substrate, CPC allows copper cables to be integrated into the system at much higher density. This not only reduces losses from PCB routing but also makes the rack’s overall cabling layout more organized and manageable.
The Formation of the CPC Supply Chain
The success of any interconnect technology ultimately depends on the maturity of its supply chain ecosystem. CPC is no exception and relies heavily on collaboration across the high-speed interconnect industry.
In the connector and high-speed cable market, companies such as Amphenol, Samtec, and TE Connectivity are among the most important participants. These firms have long supplied DAC cables, backplane connectors, and high-speed I/O modules for data centers, giving them a strong technological foundation in the CPC era.
For example, Amphenol has introduced the XtremePass CPC interconnect system, specifically designed for 224G and 448G high-speed serial signals. Its connector architecture can be mounted directly onto the package substrate and supports hundreds of differential signal channels.
The core objective of these designs is to increase package-level I/O density while maintaining signal integrity. Under certain package sizes, CPC systems can even support over one thousand differential pairs, enabling a single switching ASIC to deliver more than 100 Tbps of total bandwidth.
On the cable side, twinax cables remain the primary medium used in CPC systems. These cables provide strong shielding and low crosstalk, giving them superior performance compared with PCB traces in high-speed signal transmission.
Si-Fly® LP is Samtec's lowest profile Flyover® cable solution capable of residing adjacent to the IC package, under heat sinks or other cooling hardware with performance to 112 Gbps PAM4.
At the system level, companies such as Broadcom and Marvell Technology are among the main forces pushing CPC adoption. Both companies design data center switching silicon and work closely with cable and connector vendors to develop CPC-based interconnect architectures.
Marvell Technology has even publicly stated that its AI interconnect platform will collaborate with multiple cable and cooling partners, enabling CPC integration into future scale-up network architectures.
This type of cross-industry collaboration is gradually forming a complete CPC ecosystem, bringing together semiconductor vendors, connector manufacturers, cable suppliers, and system integrators.
TE’s AdrenaLINE Catapult 448G CPC solution designed for ultra-high-speed data transmission. By bringing interconnects closer to the silicon, it improves signal integrity and system performance. The architecture supports scalable bandwidth for next-generation data center applications.
The Cost Battle Between CPC and Optical Interconnects
In data center interconnect technologies, cost has always been one of the most critical considerations. While optical interconnects offer clear advantages in bandwidth and transmission distance, their costs remain significantly higher than those of copper interconnects.
Today, many AI data centers target an interconnect cost of roughly $0.1 per Gb/s. However, current optical modules often cost closer to $0.5 per Gb/s, highlighting a substantial cost gap between optical and electrical solutions.
For large AI clusters, this difference has major implications. When a cluster contains tens of thousands of interconnect links, even an additional cost of a few tens of dollars per link can rapidly inflate the total system cost.
It is under this cost pressure that CPC has gained increasing attention. Because its core components remain copper cables and electrical connectors, CPC can maintain high-speed interconnect performance while preserving lower overall system costs.
For hyperscalers, this means they can continue using copper interconnects in the scale-up network, while reserving optical modules for the scale-out network where long-distance communication is truly required.
This strategy allows data centers to achieve a more practical balance between performance and cost.
3月26日
CPC and the Timeline of AI Interconnect Evolution
From a technology evolution perspective, the development of data center interconnects can roughly be divided into several stages.
In early data centers, copper interconnects dominated nearly all network connections. As data rates increased, optical modules gradually became more common in rack-to-rack networking.
During the 112G PAM4 generation, copper interconnects could still cover most intra-rack connections. However, when speeds increased to 224G PAM4, the loss associated with PCB routing began to become a major challenge.
At this point, CPC emerged as a technology designed to extend the lifespan of copper interconnects.
Over the next few years, as 448G SerDes and 1.6T switches begin to appear, CPC will likely become one of the key architectures for scale-up networks.
In the longer term, as AI clusters continue to expand in scale, optical interconnects will gradually move into scale-up networks as well, forming architectures such as CPO or OIO).
In other words, CPC may represent the final major evolutionary step in the era of copper interconnects.
The Ultimate Form of Future AI Data Center Interconnects
If we extend our perspective ten years into the future, a relatively clear interconnect architecture begins to emerge.
Within chips and packages, electrical interconnects will continue to dominate, as they provide the lowest latency and lowest power consumption.
Within racks, CPC and DAC cables will continue to play a role in enabling high-speed communication between GPUs and switching ASICs.
Between racks and across data centers, optical interconnects will gradually take over the majority of communication.
This multi-layered architecture reflects a fundamental reality:
Different distances and application scenarios require different technologies.
Copper and optical interconnects are not replacements for one another; rather, they together form the layered connectivity architecture of future AI infrastructure.
A Transitional Technology in the AI Interconnect Revolution
As AI computing demand continues to surge, data center interconnect technologies are entering a period of rapid evolution. The advancement of high-speed SerDes is pushing traditional PCB-based electrical interconnects toward their physical limits, while optical interconnect technologies still face challenges related to cost and manufacturing complexity.
CPC offers a practical transitional pathway. Through innovations in packaging and cable architecture, CPC extends the lifecycle of copper interconnects in high-speed generations while paving the way for future optical connectivity.
Over the next decade, AI data center interconnect architectures will likely evolve into a multi-layered system where copper and optics coexist. In this transition, CPC will serve as one of the most important bridges connecting the copper era with the optical era of AI infrastructure.
6月18日
Previous
TopLatestDiscussions
See all