The Last Line of Defense for Copper: The Rise of Co-Packaged Copper (CPC) in AI Data Center Interconnect Architectures
The Last Line of Defense for Copper: The Rise of Co-Packaged Copper (CPC) in AI Data Center Interconnect Architectures¶
- Source: SemiVision
- Author: SEMIVISION
- Published: 2026-03-06T13:24:31+08:00
- URL: https://tspasemiconductor.substack.com/p/the-last-line-of-defense-for-copper (1) The Last Line of Defense for Copper: The Rise of Co-Packaged Copper (CPC) in AI Data Center Interconnect Architectures
The Last Line of Defense for Copper: The Rise of Co-Packaged Copper (CPC) in AI Data Center Interconnect Architectures¶
Original Article By SemiVision Research [Reading time: 15 mins]¶
Mar 06, 2026
∙ Paid
The Core Contradiction in AI Data Center Interconnects: Distance, Power, and Cost
Driven by the explosive growth of generative AI, data center interconnect technologies are entering an unprecedented turning point. As the computing capabilities of GPUs, XPUs, and custom AI accelerators continue to double year after year, the bottleneck in system architecture is gradually shifting away from the compute chips themselves toward data movement.
In other words, in the AI era, computing power is no longer determined solely by chip performance, but increasingly by how efficiently data flows within the entire cluster.
In large-scale AI training clusters, a typical system may consist of tens of thousands—or even hundreds of thousands—of accelerators. These accelerators must exchange gradients, model parameters, and intermediate results through high-speed interconnects. As model sizes and the number of training nodes continue to grow, data center networking architectures are gradually forming two distinct layers of interconnect.
The first layer is the Scale-Up network. This layer operates primarily within a single rack, connecting GPUs, CPUs, and switching ASICs so that the entire rack can function logically as a single large accelerator. Its defining characteristics are extremely high bandwidth and ultra-low latency, but the transmission distance is very short—typically a few tens of centimeters to about one meter.
The second layer is the Scale-Out network. This layer connects racks to other racks and even links multiple data centers together. Transmission distances range from a few meters to several kilometers, and the design focus shifts toward scalability and long-distance transmission.
These two networks have fundamentally different physical requirements. Scale-Up prioritizes latency and cost, while Scale-Out prioritizes bandwidth density and transmission distance. As a result, interconnect technologies are increasingly diverging into two paths: electrical interconnects for short distances and optical interconnects for longer distances.
However, as SerDes speeds enter the 200G and even 400G era, copper interconnects appear to be approaching their physical limits. Optical interconnect technologies—particularly Co-Packaged Optics (CPO)—are widely seen as the ultimate solution for future data center connectivity.
Yet before optics fully take over, a new transitional architecture is emerging within the industry:Co-Packaged Copper (CPC).
The core objective of this technology is not to replace optics, but rather to extend the lifecycle of copper interconnects in short-reach applications.
3月4日
Below we will share:
Why Copper Remains Irreplaceable in the 200G Era
The Real Limitation Is Not Copper—It Is the PCB
Co-Packaged Copper: Connecting Cables Directly to the ASIC
Broadcom and the Hyperscaler Strategy
The Boundary Between Copper and Optics Is Being Redefined
CPC vs. CPO: Two Technologies on Different Timelines
Deep Integration of CPC with AI Rack Architecture
Co-Evolution of CPC and High-Speed SerDes
Supply Chain and Ecosystem Development
The Future of Interconnect Architecture: Long-Term Coexistence of Copper and Optics
The Interconnect Architecture of the Next Decade
2月28日
Why Copper Remains Irreplaceable in the 200G Era
In many industry discussions, optical interconnects are often portrayed as rapidly replacing copper cables. In reality, the situation is far more complex. For hyperscale data centers, the choice of interconnect technology is never purely a technical decision—it is fundamentally an engineering trade-off involving cost, power consumption, and system complexity.
In a typical AI training rack, the number of connections between GPUs can easily reach hundreds or even thousands. For example, in a system containing dozens of accelerators, the internal high-speed connections within the rack alone may exceed 1,000 links. These links are usually less than one meter in length, but each may carry 800Gbps or more of bandwidth.
If all these short-distance connections were replaced with optical modules, the system’s cost and power consumption would rise dramatically. Optical modules require lasers, modulators, and photodetectors, as well as DSPs and clock recovery circuits. These components add significant power consumption and system complexity.
In contrast, passive copper cables consume virtually no power and require no additional signal processing electronics.
Within hyperscalers’ total cost models, this difference is decisive. When a data center scales to thousands of racks, even a few additional watts per connection could translate into tens of megawatts of extra power demand for the entire facility.
This is why many hyperscalers intentionally design AI system topologies so that intra-rack link distances remain within the practical reach of copper cables, reserving optical interconnects only for scenarios that truly require longer transmission distances.
That said, copper cables are not without challenges. As transmission speeds increase to 224Gbps PAM4, the biggest bottleneck is no longer the cable itself, but rather signal loss on the printed circuit board (PCB).
The Real Limitation Is Not Copper—It Is the PCB
In high-speed digital signal transmission, every segment of the signal path introduces loss. As SerDes speeds reach 200G PAM4, PCB trace insertion loss has become one of the most critical issues in channel design.
In a traditional data center switch architecture, the signal path typically looks like this:
ASIC → BGA package → PCB routing → Front-panel connector → DAC cable
Within this path, PCB routing often accounts for the majority of signal loss.
Materials such as FR-4 exhibit significant dielectric loss at high frequencies, causing signal amplitudes to decay rapidly. When channel loss becomes too high, the system must introduce active components such as retimers or equalizers to restore signal integrity.
However, these components increase power consumption, latency, and system complexity.
To address this problem, the industry has proposed a rather radical idea:
If the PCB is the problem, then bypass the PCB entirely.
This is precisely the core concept behindCo-Packaged Copper.
Co-Packaged Copper: Connecting Cables Directly to the ASIC
The concept of Co-Packaged Copper (CPC) is simple, yet its implications are far-reaching. The core idea is to connect high-speed copper cables directly to the ASIC package, rather than routing signals through the PCB.
In a CPC architecture, connectors are mounted directly on the chip’s package substrate and connected to high-speed twinax cables. This design significantly shortens the signal path and avoids the high-loss PCB traces typically found in conventional switch architectures.
By doing so, the system can support higher data rates without introducing retimers. Real-world tests have demonstrated that on Broadcom’s 224G SerDes platform, combined with Samtec CPC twinax cables, a two-meter copper channel can maintain an extremely low bit-error rate. This validates that the CPC architecture can still achieve strong signal integrity even at very high frequencies.
200G Co-Packaged Channel With Broadcom SERDES and Samtec Si-Fly HD CPC
More importantly, the CPC architecture can dramatically increase packaging density. On a 95 × 95 mm ASIC package, this design can support more than 500 channels at 200G, delivering over 100 Tbps of total bandwidth.
This means that within AI data center switches, CPC can achieve extremely high interconnect density without introducing optical modules.
Broadcom and the Hyperscaler Strategy
For network silicon vendors such as Broadcom, CPC is not merely a technological innovation—it is also a strategic market move.
2025年6月4日
Broadcom has long dominated the data center switching silicon market, with its Tomahawk and Jericho product lines forming the backbone of hyperscale network architectures. However, if future interconnect architectures shift entirely toward co-packaged optics, optical module vendors and silicon photonics companies could gain greater influence in system design.
As a result, Broadcom’s strategy is not to push optics exclusively, but to build a multi-layered interconnect architecture:
Shortest distances:Co-Packaged Copper (CPC)
Mid-range links:Active copper cables or linear optical modules
Long distances:Optical interconnects
This layered strategy allows hyperscalers to choose the most cost-effective technology for each distance range, while avoiding the premature deployment of expensive and complex optical packaging solutions.
The Boundary Between Copper and Optics Is Being Redefined
From a system architecture perspective, the emergence of CPC represents a new design philosophy.
Traditionally, data center interconnects were designed around individual devices, such as the connections between switches and servers. In the AI era, however, the design unit is gradually shifting toward entire racks—or even entire clusters.
In this new architecture, interconnect technology is no longer a single solution but rather a multi-layered combination of technologies. Copper and optical links will coexist across different distance ranges and application scenarios, forming a hybrid interconnect architecture.
CPC is a technology born precisely during this transitional period. It allows copper interconnects to remain competitive in the 224G—and even 448G—SerDes era, while simultaneously paving the way for future optical interconnect solutions.
CPC vs. CPO: Two Technologies on Different Timelines
When discussing the future of data center interconnects, the technology most frequently mentioned is Co-Packaged Optics (CPO). In this architecture, optical engines are integrated directly next to switching chips or processors, shortening electrical signal paths to just a few millimeters and eliminating the high-frequency losses associated with traditional PCB routing.
Optical interconnects offer clear advantages in bandwidth density and long-distance transmission, which is why CPO is often viewed as the ultimate solution in many technology roadmaps.
However, in real engineering and commercial deployments, the adoption of CPO has been much slower than market expectations. The reason is not that optical technology itself is unfeasible, but rather that the industry supply chain still faces several unresolved challenges. These include laser integration, fiber coupling precision, optical packaging yield, and testing processes—all critical hurdles that must be overcome before large-scale production becomes practical.
Against this backdrop, Co-Packaged Copper (CPC) is increasingly being viewed as a highly practical transitional technology.
CPC does not attempt to compete with CPO in long-distance interconnects. Instead, it focuses on short-reach Scale-Up networks within AI racks. In other words, its goal is not to replace optics with copper, but rather to extend the advantages of copper within the rack environment.
Architecturally, the difference between CPC and CPO is not merely the transmission medium. The core design philosophy of CPC is to allow high-speed signals to enter a low-loss twinax cable immediately after leaving the chip package, rather than traveling through high-loss PCB routing. This approach significantly improves signal integrity and extends the usable distance of copper interconnects in high-speed generations.
CPC optimizes short-reach intra-rack interconnects, while CPO enables long-distance optical communication between racks and across data centers.
Therefore, in AI data center interconnect architectures, CPC and CPO are not direct competitors. Instead, they operate at different layers of the system.
CPC addresses the efficiency of intra-rack electrical interconnects, while CPO is aimed at long-distance communication between racks or even across data centers.
Deep Integration of CPC with AI Rack Architecture
To understand the value of Co-Packaged Copper (CPC), one must begin with the practical design of modern AI server racks.
In next-generation AI training systems, a single rack often contains dozens of GPUs or XPUs, interconnected through high-speed links to form a tightly coupled computing unit. In some large-scale AI cluster architectures, a single rack may house tens of processors, each requiring high-speed communication with all the others.
Within such architectures, the number of intra-rack connections grows rapidly. A typical 72-accelerator rack may require more than a thousand high-speed links, with the combined cable length reaching several kilometers.
If all of these connections were implemented using optical modules, the system’s cost and power consumption would rise dramatically. For this reason, data center designers generally try to keep these short-distance connections within the electrical interconnect domain.
CPC emerged precisely in this context. By allowing cables to be routed directly from the ASIC package, CPC extends the reach of copper interconnects without requiring retimers. This not only reduces power consumption but also lowers system latency. For AI training systems that require massive GPU-to-GPU communication, these advantages are particularly important.
Even more importantly, CPC improves the overall power efficiency of the rack. Because it eliminates the need for additional signal conditioning circuits, CPC reduces power consumption between switches and servers. For large data centers, even saving a few watts per connection can translate into significant energy savings when the number of links scales to tens or hundreds of thousands.
Co-Evolution of CPC and High-Speed SerDes
The development of CPC is closely tied to the evolution of high-speed SerDes technology. Data center networking has already moved from 56G to 112G PAM4 SerDes, and the industry is now transitioning toward 224G PAM4. In the coming years, 400G and even 448G SerDes are expected to enter commercial deployment.
At these speeds, PCB trace losses increase dramatically, which is precisely why the demand for CPC grows more urgent as SerDes data rates increase.
Recent technology demonstrations have already shown that CPC architectures can support 200G-per-lane transmission. In a joint demonstration by Broadcom and Samtec, a 224G SerDes platform paired with CPC cables achieved more than 500 high-speed channels on a single package substrate, delivering over 100 Tbps of aggregate bandwidth.
Such bandwidth density means that future AI switching ASICs can still achieve extremely high I/O bandwidth while remaining within electrical interconnect architectures. For hyperscalers, this capability extends the lifespan of existing network architectures while reducing the capital pressure associated with transitioning to optical interconnects.
Supply Chain and Ecosystem Development
The development of CPC is not the result of a single company’s technological breakthrough, but rather the co-evolution of an entire industry ecosystem.
At the hardware level, CPC requires high-precision connectors and cable technologies. Companies such as Samtec, Amphenol, and TE Connectivity play critical roles in this space. These suppliers have long provided DAC cables and high-speed connectors for data centers, giving them a strong technological foundation in the CPC era.
At the silicon level, Broadcom and Marvell Technology are among the primary forces driving CPC adoption. Both companies dominate the data center switching silicon market and possess leading expertise in high-speed SerDes design. By collaborating with cable vendors and system integrators, they are helping to establish a complete CPC ecosystem.
2025年7月8日
Cooling and mechanical design companies also play important roles in CPC systems. In some demonstration platforms, CPC cables are integrated with liquid cooling systems, enabling racks to maintain adequate thermal performance while supporting high-density computing.
This cross-industry collaboration demonstrates that CPC is not merely a single technology but rather a system-level engineering effort requiring coordination across multiple supply chain segments.
The Future of Interconnect Architecture: Long-Term Coexistence of Copper and Optics
Looking at long-term trends, AI data center interconnect architectures will likely evolve into a multi-layered coexistence of technologies.
For the shortest chip-to-chip connections, high-speed electrical interconnects will remain irreplaceable. CPC is one of the core technologies at this layer. As SerDes speeds increase, CPC will be able to support higher bandwidth while maintaining low power consumption and low latency.
For mid-range interconnects, technologies such as active copper cables and linear optical modules may serve as transitional solutions. These technologies can extend transmission distance while still retaining certain cost advantages.
For long-distance interconnects, however, optical technologies will remain inevitable. Whether through pluggable optics, Linear Pluggable Optics (LPO), or Co-Packaged Optics (CPO), optical links will play an increasingly critical role in data center networks.
As a result, future AI data centers are unlikely to see a scenario in which copper is completely replaced by optics. Instead, a hybrid interconnect architecture will emerge, where different technologies coexist and operate at different distance ranges and application scenarios—each playing to its own strengths.
The Transition Era from Copper to Optics
Data center interconnect technologies in the AI era are approaching a critical turning point. As the demand for computing power continues to grow, traditional electrical interconnect architectures are facing increasing challenges, while optical interconnect technologies are gradually becoming the dominant solution for long-distance communication.
However, in this transition, copper will not disappear from the stage overnight. Through innovative architectures such as Co-Packaged Copper (CPC), copper interconnects can remain competitive in short-reach scenarios, providing the industry with a lower-cost and lower-risk pathway toward the next generation of connectivity.
For hyperscalers and networking equipment vendors, such transitional technologies carry significant strategic value. They not only extend the lifecycle of the existing electrical interconnect ecosystem, but also provide valuable time for the continued development and maturation of optical interconnect architectures.
Over the next decade, the evolution of data center interconnects is unlikely to be a single disruptive revolution. Instead, it will likely unfold as a gradual architectural evolution. In this process, CPC will play a crucial role—it is both an extension of copper interconnect technology and an important bridge leading toward the optical interconnect era.
CPC Packaging Architecture and Flyover Cable Technology
In practical engineering implementations, the core technology behind Co-Packaged Copper (CPC) is not simply connecting copper cables to the chip. Instead, it relies on a design methodology known as the Flyover Cable Architecture, which effectively allows the high-speed signal path to “fly over” traditional PCB routing.
Samtec Flyover® design provides end option flexibility to create a high-speed application-specific solution to meet next-gen speeds.
In conventional switch or GPU systems, high-speed signals exit the ASIC through BGA solder balls, pass through the package substrate, enter the PCB traces, and then connect to DAC cables through front-panel connectors. However, at 224G PAM4 data rates, the insertion loss of PCB routing has become the largest bottleneck in channel design.
CPC adopts a completely different approach. High-speed connectors are placed directly near the package substrate, allowing signals to enter twinax cables immediately after leaving the chip package, bypassing long PCB routing paths. This design significantly reduces signal loss and minimizes crosstalk.
Under this architecture, the signal path becomes:
ASIC
→ Package substrate routing
→ CPC connector
→ Twinax cable
→ Front-panel connector
Through this design, the total channel insertion loss can be dramatically reduced.
In experimental platforms jointly demonstrated by Broadcom and Samtec, a 224G SerDes platform paired with the Si-Fly HD CPC cable system achieved 512 lanes of 200G interconnects on a 95 × 95 mm package substrate, delivering a total bandwidth of 102.4 Tbps.
This means a single switching ASIC can achieve I/O bandwidth equivalent to a 102.4T switch while still relying on electrical interconnects.
For hyperscalers, this capability is critical. It allows intra-rack connectivity to continue using low-cost copper cables, avoiding the immediate need to adopt expensive and complex optical modules.
Scale-Up Networks: The Real Battlefield of AI Clusters
When discussing AI data center interconnects, attention often focuses on the fiber networks connecting racks. However, the factor that truly determines AI system performance is often the Scale-Up network.
In large AI training clusters, data exchange between GPUs occurs far more frequently than communication between racks. Operations such as gradient synchronization, model sharding, and parameter updates require massive GPU-to-GPU communication. As a result, GPU-to-GPU interconnect bandwidth often needs to reach hundreds of gigabytes per second.
In early GPU clusters, these interconnects were typically implemented using PCIe or NVLink cables. But as AI systems scale, the number of GPUs within a single rack has increased rapidly. Systems such as NVIDIA NVL72 provide a representative example.
In such systems, a single rack may contain dozens of GPUs, each requiring high-frequency communication with every other GPU. This dramatically increases the number of intra-rack connections.
In some AI rack designs, the number of internal links can exceed 1,300 high-speed connections.
If all of these links were implemented using optical modules, the total system cost would quickly become prohibitive.
Therefore, hyperscalers often intentionally limit GPU-to-GPU distances to around one meter when designing AI cluster topologies so that copper interconnects can still be used.
This is precisely where CPC technology becomes most valuable: in AI Scale-Up networks.
CPC and Hyperscaler System Strategy
From an industry perspective, the rise of CPC reflects a broader system-level strategy adopted by hyperscalers:
Reserve optics for the places where long-distance transmission is truly required.
In hyperscale data centers operated by companies such as Google, Meta Platforms, and Microsoft, network architectures are typically divided into three layers:
Chip-to-Chip Fabric
Examples include NVLink or UCIe, enabling high-speed communication between processors or accelerators.
Rack-Scale Network
This layer primarily connects GPUs to switching ASICs within the rack.
Cluster Network
This layer handles communication between racks or across data center clusters.
Among these three layers, optical interconnects are primarily deployed in the third layer—the scale-out network.
In contrast, electrical interconnects still hold significant advantages in the first and second layers.
The design philosophy of Co-Packaged Copper is built precisely around this architecture. It enables high-speed electrical interconnects to remain viable in the 224G—and even 448G—SerDes generations, without prematurely forcing the adoption of optical solutions.
CPC and the Evolution of SerDes: The 224G and 448G Generations
The future evolution of data center interconnect technology will largely depend on the pace of SerDes development.
Today’s mainstream switching ASICs have already entered the 112G PAM4 generation, while the next step is 224G PAM4.
At these data rates, traditional PCB routing can no longer maintain adequate signal integrity, making new packaging and interconnect architectures increasingly unavoidable.
Co-Packaged Copper (CPC) is one of the key solutions emerging in response.
By connecting cables directly to the package substrate, CPC significantly reduces channel loss and extends the practical distance of copper interconnects.
This enables 224G lanes to operate reliably over distances of roughly 1–2 meters.
Looking ahead, as 448G SerDes begins to emerge, the importance of this package–interconnect integration architecture will become even more pronounced.
The Limits of Copper and the Inevitability of Optics
Although CPC can extend the lifespan of copper interconnects, copper still faces fundamental physical limitations.
At high frequencies, electrical signals are affected by skin effect and dielectric loss, which lead to signal attenuation and phase distortion. As data rates increase, these challenges become increasingly severe.
Research suggests that with passive copper cables, the practical reach of high-speed electrical interconnects typically does not exceed about one meter. Beyond that distance, systems must introduce retimers or optical links.
This is why optical interconnects remain the long-term direction for data center networking.
Future AI clusters may contain hundreds of thousands—or even millions—of GPUs, and systems of that scale will inevitably require high-density optical interconnects to sustain communication bandwidth.
The Interconnect Architecture of the Next Decade
Based on current technology trends, future data centers are likely to adopt a multi-layered interconnect architecture.
Within chips and packages, high-speed electrical interconnects will remain the optimal solution.
Within racks, CPC and DAC cables will continue to dominate the scale-up network.
Between racks, optical modules and co-packaged optics (CPO) will gradually become the mainstream technology.
This hybrid interconnect architecture will continue evolving over the next decade, adapting to the growing scale and complexity of AI systems.
Copper Will Not Disappear—It Will Change Its Role
In many technology forecasts, optical interconnects are often portrayed as replacements for copper. However, from a system engineering perspective, the two are more likely to coexist over the long term.
The emergence of Co-Packaged Copper demonstrates that copper interconnects still possess significant engineering value. Through innovations in packaging and cable architecture, copper can continue to provide low-cost, low-power, and low-latency connectivity in short-reach scenarios.
For hyperscalers, this means they can gradually transition toward optical interconnects without completely redesigning their network architecture.
In other words, CPC is not a competitor to optical interconnects—it is a bridge that helps AI data centers move from the “era of copper” to the “era of optics.”
2025年7月25日
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