2026 NVIDIA: 6 Chips for the Next Generation of AI Data Centers
2026 NVIDIA: 6 Chips for the Next Generation of AI Data Centers¶
- Source: SemiVision
- Author: SEMIVISION
- Published: 2026-02-26T21:24:39+08:00
- URL: https://tspasemiconductor.substack.com/p/2026-nvidia-6-chips-for-the-next (1) 2026 NVIDIA: 6 Chips for the Next Generation of AI Data Centers
2026 NVIDIA: 6 Chips for the Next Generation of AI Data Centers¶
Original Article By SemiVision Reserach [Reading time: 10 mins]¶
Feb 26, 2026
∙ Paid
Extreme Co-Design of the Vera Rubin Platform — “The Rack Is the Computer”
Six Silicon Products Form a System-Level Stronghold
The true strategy of the Rubin platform is not single-GPU performance, but the integration of six silicon products into a unified system:
Rubin GPU
Vera CPU
NVLink 6 Switch
ConnectX-9 SuperNIC
BlueField-4 DPU
Spectrum-6 Ethernet Switch
According to official disclosures, a Vera Rubin NVL72 rack consists of 72 Rubin GPUs and 36 Vera CPUs. Through NVLink 6, GPU-to-GPU bandwidth reaches 3.6 TB/s per GPU and 260 TB/s per rack. Vera CPUs and Rubin GPUs are connected via second-generation NVLink C2C, delivering 1.8 TB/s of coherent interconnect bandwidth.
This architecture makes it clear that NVIDIA is no longer selling GPUs as standalone products. Instead, it is commercializing a rack-scale AI factory unit, bringing CPUs, GPUs, switches, NICs, DPUs, and even Ethernet switches entirely into its own product stack. This system-level integration makes it extremely difficult for competitors to disrupt performance or total cost of ownership (TCO) by attacking any single component in isolation.
System-Level Design Priorities
Co-design:The functions and pinouts of all silicon components are coordinated at the design stage, rather than relying on software to compensate for hardware bottlenecks later. This system-level co-design tightly aligns the timing and protocols of NVLink 6, ConnectX-9, and BlueField-4, forming a single rack-scale compute unit.
Unified packaging:The Superchip packages two Rubin GPUs and one Vera CPU on a single board, directly interconnected via NVLink C2C, providing a tightly coupled heterogeneous computing platform for rack-scale systems.
Strategic product positioning:By controlling six major silicon domains—compute, memory, communications, storage, power, and networking—NVIDIA can define rack-level system specifications and supply-chain pathways. This shifts customers toward template-based racks rather than one-off customized equipment, establishing system-level dominance.
Rubin GPU: Built for Low-Precision Throughput and Bandwidth
The Rubin GPU is not simply about adding more transistors; it is purpose-built for low-precision inference and extreme bandwidth.
NVFP4 / NVFP8: Quantization as the Core Battleground
Rubin adopts the third-generation Transformer Engine, supporting low-precision formats such as NVFP4 and NVFP8. NVIDIA states that each Rubin GPU delivers up to 50 PFLOPS NVFP4 for inference and 35 PFLOPS NVFP4 for training.
As precision drops, hardware performance is no longer determined by headline FLOPS alone, but becomes tightly coupled to quantization strategy and kernel optimization. End-to-end metrics such as model FLOP utilization (MFU), tokens per second, and network convergence efficiency become the real benchmarks.
Low precision therefore demands deep coordination between software and system engineering—from PTQ/QAT quantization pipelines, to token-processing kernels, to highly optimized all-to-all collectives.
HBM4 and Aggressive Bandwidth Scaling
Rubin is the first GPU platform to integrate HBM4 memory directly into the GPU package. Each card is equipped with 288 GB of HBM4, delivering approximately 22 TB/s of memory bandwidth. This represents a major leap over the Blackwell generation’s HBM3e, driven primarily by doubling the bus width and higher pin speeds.
This bandwidth jump significantly increases signal and power integrity (SI/PI) challenges, as well as DRAM yield and thermal demands at the packaging level. For the supply chain, HBM4 yield and packaging cycle time are likely to become critical bottlenecks.
Productizing the Power Curve
Rubin GPUs are offered with two power envelopes: 2300 W (Max P) and 1800 W (Max Q). This effectively productizes the most constrained resources in modern data centers—power and cooling capacity.
Vera CPU: An In-House CPU as the Memory Hub and Control Plane
The Vera CPU is built on 88 in-house Olympus ARM cores, purpose-designed for AI factories. It is not merely a compute element, but a memory and control hub:
NVLink C2C coherence domain:Vera connects to Rubin via NVLink C2C, delivering 1.8 TB/s of coherent bandwidth. This allows HBM4 and LPDDR5X (SOCAMM) to form a logically unified memory pool, enabling the CPU to provide GPUs with larger addressable memory space and coherent data management.
Expanded DRAM capacity:Vera can be populated with large amounts of LPDDR5X SOCAMM as a capacity tier beyond HBM4, used for model weights, KV cache, or system state. This reduces reliance on external memory accessed via PCIe/CXL.
Return to in-house design:With Vera, NVIDIA regains control over the instruction set, microarchitecture, and I/O chiplets, allowing deep optimization of cores, caches, and memory controllers for AI-factory workloads—moving away from the constraints of general-purpose x86 designs.
NVLink 6 Switch: The Scale-Up Backbone for Interconnect Density and Reliability
Compared with NVLink 5, NVLink 6 doubles per-GPU interconnect bandwidth to 3.6 TB/s, with total rack bandwidth reaching 260 TB/s. More important than raw bandwidth is the interconnect architecture itself:
Bidirectional SerDes with echo cancellation:NVLink 6 enables bidirectional transmission over the same signal pairs, requiring sophisticated echo cancellation and equalization, but eliminating the need to double cable counts. This reduces interconnect points and improves assembly yield.
In-network compute:NVLink 6 switches support executing portions of collective operations directly within the network, offloading all-reduce, shuffle, and similar workloads from GPUs. This accelerates MoE routing and large-scale model training.
Production-grade reliability and blind-mate serviceability:Rubin’s NVLink switch trays integrate four NVLink 6 chips per module, using board-to-board connectors that support hot and cold swapping with zero downtime. This replaces large numbers of high-speed cables with robust connectors and PCBs, significantly reducing on-site wiring errors.
ConnectX-9 and BlueField-4: From Endpoint Control to Infrastructure Operations
Rubin’s scale-out capability is anchored by the ConnectX-9 SuperNIC and BlueField-4 DPU. Each Rubin GPU is paired with four ConnectX-9 NICs, delivering up to 1.6 Tb/s of network bandwidth per GPU. Key innovations include:
ConnectX-9: The Endpoint as a Network Scheduler
Programmable congestion control:In MoE inference, where hundreds of GPUs may transmit simultaneously and create transient congestion, ConnectX-9 performs traffic shaping and scheduling at the endpoint, smoothing bursts and reducing head-of-line blocking.
Multi-tenant isolation:Hardware-level fair scheduling and security mechanisms ensure that workloads from different tenants do not interfere with one another.
High security:Integrated encryption engines support IPsec/PSP, enabling both data-in-transit and data-at-rest encryption.
BlueField-4: The Operating System of the AI Factory
BlueField-4 integrates a 64-core Grace CPU, LPDDR5X memory controllers, and ConnectX-9 networking, providing 250 GB/s of memory bandwidth and 800 Gb/s of network bandwidth. It serves as the infrastructure control plane:
Control and security isolation:Through ASTRA (Advanced Secure Trusted Resource Architecture), BlueField-4 establishes a single root of trust, enabling secure isolation and trusted deployment in multi-tenant AI factories.
Infrastructure offload:Storage, networking, and security tasks are offloaded to the DPU, freeing CPUs and GPUs to focus on AI computation.
KV-cache storage:Announced at CES 2026, theInference Context Memory Storage Platformmoves KV cache into a storage tier built on BlueField-4 and Spectrum X, delivering 5× higher tokens/s and 5× TCO efficiency for inference memory.
Spectrum-6 and CPO: Advancing Ethernet Through Co-Packaged Optics
Rubin’s scale-across strategy is powered by Spectrum-6 Ethernet, leveraging 200 G SerDes and Co-Packaged Optics (CPO). Developer documentation notes that Spectrum X Ethernet Photonics, via co-packaged silicon photonics engines, achieves 5× lower power per 1.6 Tb/s port, 5× higher mean time between failures, and 10× greater network resilience. Key innovations include:
512-lane 200 G CPO architecture:The SN6800/SN6810 switches integrate 512 lanes of 200 G SerDes with photonic engines, delivering 409.6 Tb/s of total bandwidth. Built-in optical shuffle mechanisms maintain low latency as GPU clusters scale.
Dual-track strategy: pluggable + CPO:While CPO offers clear advantages in density and power efficiency, pluggable optics still excel in serviceability, spare-parts logistics, and supply-chain maturity. In the near term, ultra-high-density deployments (such as large radix switches) will adopt CPO first, while mainstream switches will continue to blend pluggable modules to balance yield and maintainability.
Cableless Compute Trays: From Cables to Board-to-Board Interconnects
One of the most significant breakthroughs of Rubin NVL72 is its cableless, modular compute tray design. Each tray integrates two Vera Rubin superchips, NVLink 6 spine connectors, BlueField-4 DPU, and ConnectX-9 SuperNICs, completely eliminating internal high-speed cables. Instead, the tray plugs directly into the rack via board-to-board connectors. Key characteristics include:
18× reduction in assembly time:Assembling a single GB300 NVL72 tray takes roughly 100 minutes, whereas Rubin’s cableless tray requires only about 5 minutes.
High-performance density:Each tray delivers 200 PFLOPS NVFP4 compute, 14.4 TB/s of NVLink 6 bandwidth, 2 TB of high-speed memory, 1.6 Tb/s of network bandwidth per GPU, and 800 Gb/s of DPU bandwidth, effectively reaching the level where “the rack is the computer.”
Rising value of board-to-board connectors:High-speed interconnects shift from flexible cables to rigid PCBs and connectors, imposing extremely demanding requirements on connector density, mating-cycle durability, and impedance control. This transition also drives demand for advanced PCB materials and automated insertion mechanisms.
1月31日
PCB Materials and Signal Integrity: M8/M9, HVLP, and Quartz Glass
Rubin’s cableless design forces high-frequency signals to traverse long distances on PCBs, placing much stricter demands on copper foil, resin systems, and fiberglass fabrics:
From M8 to M9:PCB materials targeting 224 Gb/s (1.6 T) transmission must evolve from M8 to M8.5–M9. Analyses indicate that M9 primarily uses quartz fiber fabric, which has already been adopted in Rubin’s CPX boards and midplanes. Quartz fabric offers lower dielectric constant and lower coefficient of thermal expansion, but comes with significantly higher material cost and manufacturing complexity.
HVLP4 copper foil:Both M8 and M9 commonly use HVLP4 (Hyper Very Low Profile) copper foil, whose reduced surface roughness lowers conductor loss and crosstalk. Market forecasts suggest a widening supply–demand gap for HVLP4; by 2026, demand may exceed 3,000 tons per month, while supply expansion remains slow.
Design imperatives:PCB materials must balance low loss and thermal robustness, while supporting 20–36+ layer stack-ups and heavy copper routing. Signal integrity (SI), power integrity (PI), and blind-mate board-to-board interconnects are tightly coupled; incorrect material choices can lead to excessive insertion loss, eye-diagram collapse, or elevated board temperatures—ultimately compromising system reliability.
2025年10月27日
2025年7月30日
2025年7月6日
Cooling and Power Delivery: New Infrastructure with 45 °C Warm Water and 800 V HVDC
Warm-Water Liquid Cooling: From Refrigeration to Hydraulics
NVIDIA states that Rubin NVL72 adopts single-phase direct liquid cooling with a 45 °C supply temperature, eliminating chillers in most climates and relying instead on dry coolers for heat rejection. Data centers are thus shifting from “cold-storage-style” environments to warm-water circulation. Key physical implications include:
Expanded ΔT:A 45 °C inlet and 65 °C outlet provide a ΔT of ~20 °C, reducing required flow rates, shrinking pipe diameters, and lowering pump power. Athree-loop architectureis used: outdoor FWS, cooling distribution units (CDUs), and compute-side thermal control systems (TCS). Cooling priorities therefore move away from chillers toward pumps, piping, quick disconnects, and water-quality management.
Supply-chain shift:Cooling hardware value migrates from condensers to CDUs, manifolds, pumps, and water-treatment systems. Operating at 45 °C increases risks of biofouling and corrosion, driving demand for water-chemistry solutions and high-reliability quick-disconnect connectors.
2月10日
800 V HVDC: A Power Infrastructure Reset
With rack power density exceeding 200 kW, traditional 54 V DC distribution can no longer handle the resulting currents and copper losses. NVIDIA proposes an 800 V HVDC architecture, rectifying 13.8 kV AC to 800 V DC in the substation and delivering it directly to racks via busbars, with only a single step-down inside the rack to reach GPU core voltages. Benefits include:
~45% reduction in copper usage and ~5% improvement in overall power efficiency;
Fewer conversion stages and reduced copper loss, improving the economics of 1 MW-class racks;
Cooling synergy: Combining HVDC with warm-water liquid cooling turns high-power racks into robust electrical-and-hydraulic engineering systems, rather than refrigeration problems.
From Customization to Templates: ODM and Supply-Chain Reshaping
The Rubin platform consolidates hyperscaler flexibility into NVIDIA-defined, template-based delivery. Racks and compute trays use standardized dimensions, blind-mate interfaces, and modular designs, allowing OEMs/ODMs to manufacture strictly to reference designs—without extensive custom cabling or bespoke boards. Outcomes include:
Automated assembly:ODMs capable of blind-mate, rapid assembly—supported by automated lines and precision fixtures—will gain share, while firms reliant on manual cabling and hand soldering are phased out.
Value redistribution:Supply-chain value shifts from traditional “custom cables/custom boards” to high-density connectors, advanced PCB materials, and modular mechanical components. Vendors supplying HVLP4 copper foil, M9 laminates, blind-mate connectors, and liquid-cooling quick disconnects emerge as primary beneficiaries.
Serviceability and RAS:Rubin introduces a second-generation RAS engine and cableless modules, enabling NVLink switch trays to be replaced without taking racks offline. Customers follow NVIDIA’s maintenance templates rather than designing their own processes—further strengthening supply-chain control.
TCO and Economics: Higher GPU Cost, Lower Token Cost
Media reports highlight the Rubin platform’s compelling economics for MoE training and inference:
10× lower inference token costand4× fewer GPUs requiredfor MoE training.StorageReviewnotes that VR NVL72 delivers inference token costs at one-seventh of Blackwell, requires one-quarter the GPUs to train comparable large MoE models, and improves compute efficiency by 8× per watt.
Faster deployment cadence:Modular VR NVL72 reduces rack assembly time by18×, sharply cutting deployment time and labor cost—especially critical during supply-constrained periods.
End-to-end ecosystem:BlueField-4’s ASTRA and third-generation Confidential Computing enable end-to-end isolation across the NVL72 rack. Spectrum X Photonics, via CPO, delivers 5× power efficiency and 10× resilience, increasing system uptime.
In sum, while Rubin racks may carry higher unit costs due to advanced PCB materials, liquid cooling, and HVDC, the gains in token cost, deployment efficiency, and operational stability reduce overall TCO—while strengthening NVIDIA’s pricing power and control over the supply chain.
2月26日
2025年5月10日
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